From 00ecb871c4bfb7b83519704d274b4a59a6fa38f4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Sep 2019 12:37:05 +0200
Subject: [PATCH] gen: add separators

---
 litedram/gen.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/litedram/gen.py b/litedram/gen.py
index 7856df0..61722ac 100644
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -45,6 +45,7 @@ from litedram.frontend.axi import *
 from litedram.frontend.bist import LiteDRAMBISTGenerator
 from litedram.frontend.bist import LiteDRAMBISTChecker
 
+# IOs/Interfaces -----------------------------------------------------------------------------------
 
 def get_common_ios():
     return [
@@ -178,6 +179,7 @@ class Platform(XilinxPlatform):
     def __init__(self):
         XilinxPlatform.__init__(self, "", io=[], toolchain="vivado")
 
+# CRG ----------------------------------------------------------------------------------------------
 
 class LiteDRAMCRG(Module):
     def __init__(self, platform, core_config):
@@ -213,6 +215,7 @@ class LiteDRAMCRG(Module):
         iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
 
+# Core ---------------------------------------------------------------------------------------------
 
 class LiteDRAMCoreControl(Module, AutoCSR):
     def __init__(self):
@@ -370,6 +373,7 @@ class LiteDRAMCore(SoCSDRAM):
         else:
             raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))
 
+# Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteDRAM standalone core generator")