From 4815be2feffb355af3e714a069741742c01c139d Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Sun, 30 Oct 2022 10:18:49 +0100 Subject: [PATCH 1/2] Add new module MT46H128M16 --- litedram/modules.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/litedram/modules.py b/litedram/modules.py index 6d215ee..af517b1 100755 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -590,6 +590,14 @@ class MT46H64M16(LPDDRModule): technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None) speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)} +class MT46H128M16(LPDDRModule): + # geometry + nbanks = 4 + nrows = 16384 + ncols = 2048 + # timings + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None) + speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)} class MT46H32M32(LPDDRModule): # geometry From cf893a98399b4cf279e5b66dc144e4b798210029 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Sun, 30 Oct 2022 13:17:51 +0100 Subject: [PATCH 2/2] Bankmaschine: Don't use A10 for col addresses. A10 is reserved for auto precharge. For memories with more than 1024 cols (>10bit) A[0:9] and A[11:] is used. I tested this with MT46H128M16. --- litedram/core/bankmachine.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 55512bc..144929d 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -34,7 +34,10 @@ class _AddressSlicer: def col(self, address): split = self.colbits - self.address_align - return Cat(Replicate(0, self.address_align), address[:split]) + if self.colbits>10: # A10 is reserved for auto-precharge, this bit needs to be skipped for col addresses + return Cat(Replicate(0, self.address_align), address[:10-self.address_align], 0, address[10-self.address_align:split]) + else: + return Cat(Replicate(0, self.address_align), address[:split]) # BankMachine --------------------------------------------------------------------------------------