diff --git a/bench/genesys2.py b/bench/genesys2.py
index 6013acf..e483229 100755
--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -22,6 +22,8 @@ from litex.soc.integration.builder import *
 from litedram.phy import s7ddrphy
 from litedram.modules import MT41J256M16
 
+from liteeth.phy.s7rgmii import LiteEthPHYRGMII
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module, AutoCSR):
@@ -86,6 +88,14 @@ class BenchSoC(SoCCore):
         # UARTBone ---------------------------------------------------------------------------------
         self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
 
+        # Etherbone --------------------------------------------------------------------------------
+        self.submodules.ethphy = LiteEthPHYRGMII(
+            clock_pads         = self.platform.request("eth_clocks"),
+            pads               = self.platform.request("eth"),
+            with_hw_init_reset = False)
+        self.add_csr("ethphy")
+        self.add_etherbone(phy=self.ethphy)
+
         # Leds -------------------------------------------------------------------------------------
         from litex.soc.cores.led import LedChaser
         self.submodules.leds = LedChaser(
@@ -97,9 +107,11 @@ class BenchSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteDRAM Bench on Genesys2")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--test",  action="store_true", help="Run Test")
+    parser.add_argument("--build",       action="store_true", help="Build bitstream")
+    parser.add_argument("--load",        action="store_true", help="Load bitstream")
+    parser.add_argument("--load-bios",   action="store_true", help="Load BIOS")
+    parser.add_argument("--set-sys-clk", default=None,        help="Set sys_clk")
+    parser.add_argument("--test",        action="store_true", help="Run Full Bench")
     args = parser.parse_args()
 
     soc     = BenchSoC()
@@ -110,6 +122,14 @@ def main():
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
+    if args.load_bios is not None:
+        from common import s7_load_bios
+        s7_load_bios("build/genesys2/software/bios/bios.bin")
+
+    if args.set_sys_clk is not None:
+        from common import s7_set_sys_clk
+        s7_set_sys_clk(clk_freq=float(args.config), vco_freq=soc.crg.main_pll.compute_config()["vco"])
+
     if args.test:
         from common import s7_bench_test
         s7_bench_test(