From 04334ae141cd3774dcabd524fc521355c3b95af5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 30 Mar 2021 08:51:44 +0200 Subject: [PATCH] phy/s7ddrphy/usddrphy: Use explicit sys clock domain on ClockSignal/ResetSignal. Improve readability. --- litedram/phy/s7ddrphy.py | 36 ++++++++++++++++++------------------ litedram/phy/usddrphy.py | 24 ++++++++++++------------ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index d2a515f..3f1c27d 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -129,9 +129,9 @@ class S7DDRPHY(Module, AutoCSR): p_TRISTATE_WIDTH = 1, p_DATA_RATE_OQ = "DDR", p_DATA_RATE_TQ = "BUF", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), **{f"i_D{n+1}": (0b10101010 >> n) & 0b1 for n in range(8)}, o_OQ = sd_clk_se_nodelay, i_OCE = 1, @@ -146,7 +146,7 @@ class S7DDRPHY(Module, AutoCSR): p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6, p_ODELAY_TYPE = "VARIABLE", p_ODELAY_VALUE = 0, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = self._cdly_rst.re | self._rst.storage, i_LDPIPEEN = 0, i_CE = self._cdly_inc.re, @@ -187,9 +187,9 @@ class S7DDRPHY(Module, AutoCSR): p_TRISTATE_WIDTH = 1, p_DATA_RATE_OQ = "DDR", p_DATA_RATE_TQ = "BUF", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), **{f"i_D{n+1}": getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)}, i_OCE = 1, o_OQ = oq if with_odelay else pad[i], @@ -204,7 +204,7 @@ class S7DDRPHY(Module, AutoCSR): p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6, p_ODELAY_TYPE = "VARIABLE", p_ODELAY_VALUE = 0, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = self._cdly_rst.re | self._rst.storage, i_LDPIPEEN = 0, i_CE = self._cdly_inc.re, @@ -242,9 +242,9 @@ class S7DDRPHY(Module, AutoCSR): p_TRISTATE_WIDTH = 1, p_DATA_RATE_OQ = "DDR", p_DATA_RATE_TQ = "BUF", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk) if with_odelay else ClockSignal(ddr_clk+"_dqs"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), **{f"i_D{n+1}": dqs_bitslip.o[n] for n in range(8)}, i_OCE = 1, o_OFB = dqs_o_no_delay if with_odelay else Signal(), @@ -263,7 +263,7 @@ class S7DDRPHY(Module, AutoCSR): p_PIPE_SEL = "FALSE", p_ODELAY_TYPE = "VARIABLE", p_ODELAY_VALUE = half_sys8x_taps, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = (self._dly_sel.storage[i] & self._wdly_dqs_rst.re) | self._rst.storage, i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re, i_LDPIPEEN = 0, @@ -294,9 +294,9 @@ class S7DDRPHY(Module, AutoCSR): p_TRISTATE_WIDTH = 1, p_DATA_RATE_OQ = "DDR", p_DATA_RATE_TQ = "BUF", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), **{f"i_D{n+1}": dm_o_bitslip.o[n] for n in range(8)}, i_OCE = 1, o_OQ = dm_o_nodelay if with_odelay else pads.dm[i], @@ -311,7 +311,7 @@ class S7DDRPHY(Module, AutoCSR): p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6, p_ODELAY_TYPE = "VARIABLE", p_ODELAY_VALUE = 0, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage, i_LDPIPEEN = 0, i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re, @@ -344,9 +344,9 @@ class S7DDRPHY(Module, AutoCSR): p_TRISTATE_WIDTH = 1, p_DATA_RATE_OQ = "DDR", p_DATA_RATE_TQ = "BUF", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), **{f"i_D{n+1}": dq_o_bitslip.o[n] for n in range(8)}, i_TCE = 1, i_T1 = ~dq_oe_delay.output, @@ -366,10 +366,10 @@ class S7DDRPHY(Module, AutoCSR): p_DATA_RATE = "DDR", p_NUM_CE = 1, p_IOBDELAY = "IFD", - i_RST = ResetSignal() | self._rst.storage, + i_RST = ResetSignal("sys") | self._rst.storage, i_CLK = ClockSignal(ddr_clk), i_CLKB = ~ClockSignal(ddr_clk), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_BITSLIP = 0, i_CE1 = 1, i_DDLY = dq_i_delayed, @@ -387,7 +387,7 @@ class S7DDRPHY(Module, AutoCSR): p_PIPE_SEL = "FALSE", p_ODELAY_TYPE = "VARIABLE", p_ODELAY_VALUE = 0, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re)| self._rst.storage, i_LDPIPEEN = 0, i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re, @@ -404,7 +404,7 @@ class S7DDRPHY(Module, AutoCSR): p_PIPE_SEL = "FALSE", p_IDELAY_TYPE = "VARIABLE", p_IDELAY_VALUE = 0, - i_C = ClockSignal(), + i_C = ClockSignal("sys"), i_LD = (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage, i_LDPIPEEN = 0, i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re, diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 7a0351f..312d6c8 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -144,7 +144,7 @@ class USDDRPHY(Module, AutoCSR): p_IS_CLKDIV_INVERTED = 0, i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_D = 0b10101010, o_OQ = clk_o_nodelay, ), @@ -157,7 +157,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage, - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, i_INC = 1, @@ -205,7 +205,7 @@ class USDDRPHY(Module, AutoCSR): p_IS_CLKDIV_INVERTED = 0, i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_D = Cat(*[getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)]), o_OQ = o_nodelay, ), @@ -218,7 +218,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage, - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, i_INC = 1, @@ -271,7 +271,7 @@ class USDDRPHY(Module, AutoCSR): p_IS_CLKDIV_INVERTED = 0, i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_T = ~dqs_oe_delay.output, i_D = dqs_bitslip.o, o_OQ = dqs_nodelay, @@ -289,7 +289,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_VALUE = int(tck*1e12/4), o_CNTVALUEOUT = self._half_sys8x_taps.status if (i == 0) and (j == 0) else Signal(), i_RST = ResetSignal("ic"), - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re, i_INC = 1, @@ -330,7 +330,7 @@ class USDDRPHY(Module, AutoCSR): p_IS_CLKDIV_INVERTED = 0, i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_D = dm_o_bitslip.o, o_OQ = dm_o_nodelay, ), @@ -346,7 +346,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_VALUE = 0, i_RST = ResetSignal("ic") | (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage, i_EN_VTC = self._en_vtc.storage, - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re, i_INC = 1, i_ODATAIN = dm_o_nodelay, @@ -380,7 +380,7 @@ class USDDRPHY(Module, AutoCSR): p_IS_CLKDIV_INVERTED = 0, i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_D = dq_o_bitslip.o, i_T = ~dq_oe_delay.output, o_OQ = dq_o_nodelay, @@ -399,7 +399,7 @@ class USDDRPHY(Module, AutoCSR): i_RST = ResetSignal("ic") | self._rst.storage, i_CLK = ClockSignal("sys4x"), i_CLK_B = ClockSignal("sys4x"), # locally inverted - i_CLKDIV = ClockSignal(), + i_CLKDIV = ClockSignal("sys"), i_D = dq_i_delayed, i_FIFO_RD_EN = 0, o_Q = dq_i_bitslip.i, @@ -417,7 +417,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re) | self._rst.storage, - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re, i_INC = 1, @@ -436,7 +436,7 @@ class USDDRPHY(Module, AutoCSR): p_DELAY_TYPE = "VARIABLE", p_DELAY_VALUE = 0, i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage, - i_CLK = ClockSignal(), + i_CLK = ClockSignal("sys"), i_EN_VTC = self._en_vtc.storage, i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re, i_INC = 1,