From 04717b478bbd835ddbc95badb246a2f923cb8b8d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:59:01 +1000 Subject: [PATCH] gen: Rename standalone core wishbone Name it wb_ctrl rather than just wb, which makes the resulting core signal names a bit more descriptive. IE. The DRAM control bus (by opposition to the use/data buss(es). Signed-off-by: Benjamin Herrenschmidt --- litedram/gen.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index 713914c..7acbaf0 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -381,10 +381,10 @@ class LiteDRAMCore(SoCCore): ] if cpu_type is None: # Expose bus interface to user. - wb_bus = wishbone.Interface() + wb_bus = wishbone.Interface(adr_width = self.csr.address_width) self.bus.add_master(master=wb_bus) - platform.add_extension(wb_bus.get_ios("wb")) - wb_pads = platform.request("wb") + platform.add_extension(wb_bus.get_ios("wb_ctrl")) + wb_pads = platform.request("wb_ctrl") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") # User ports -------------------------------------------------------------------------------