diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index bd8c7bc..0bd8581 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -62,9 +62,6 @@ class LiteDRAMController(Module):
             bank_machines.append(bank_machine)
             self.submodules += bank_machine
             self.comb += getattr(self.interface, "bank"+str(i)).connect(bank_machine.req)
-            # FIXME: simulation workaround
-            if phy_settings.memtype == "DDR3" and phy_settings.nphases == 2:
-                self.comb += bank_machine.req.adr[-1].eq(0)
 
         self.submodules.multiplexer = Multiplexer(settings,
                                                   bank_machines,