From 05ed5bf59d31029d3f91c5a348cdd539a150631b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 30 Sep 2020 19:39:10 +0200
Subject: [PATCH] phy/ecp5ddrphy: simplify using new get_sys_phase.

---
 litedram/phy/ecp5ddrphy.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py
index 8a15f92..e6ecbde 100644
--- a/litedram/phy/ecp5ddrphy.py
+++ b/litedram/phy/ecp5ddrphy.py
@@ -122,8 +122,8 @@ class ECP5DDRPHY(Module, AutoCSR):
         self.datavalid = Signal(databits//8)
 
         # PHY settings -----------------------------------------------------------------------------
-        rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
-        wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
+        rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
+        wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
         self.settings = PhySettings(
             phytype       = "ECP5DDRPHY",
             memtype       = memtype,
@@ -133,11 +133,11 @@ class ECP5DDRPHY(Module, AutoCSR):
             nphases       = nphases,
             rdphase       = rdphase,
             wrphase       = wrphase,
-            rdcmdphase    = rdcmdphase,
-            wrcmdphase    = wrcmdphase,
+            rdcmdphase    = (rdphase - 1)%nphases,
+            wrcmdphase    = (wrphase - 1)%nphases,
             cl            = cl,
             cwl           = cwl,
-            read_latency  = 2 + cl_sys_latency + 2 + log2_int(4//nphases) + 5,
+            read_latency  = cl_sys_latency + 10,
             write_latency = cwl_sys_latency
         )