From 06ca898c698548ba17117ee6b5701e4ac2121bc8 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Fri, 20 Aug 2021 11:24:49 +0800 Subject: [PATCH] litedram_gen: Add ECLKBRIDGECS for ECP5 clock Signed-off-by: Matt Johnston --- litedram/gen.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 372a9aa..06fb4da 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -317,14 +317,19 @@ class LiteDRAMECP5DDRPHYCRG(Module): self.sync.por += If(~por_done, por_count.eq(por_count - 1)) # PLL. + sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(~por_done | rst | self.rst) pll.register_clkin(clk, core_config["input_clk_freq"]) pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"]) pll.create_clkout(self.cd_init, core_config["init_clk_freq"]) self.specials += [ + Instance("ECLKBRIDGECS", + i_CLK0 = self.cd_sys2x_i.clk, + i_SEL = 0, + o_ECSOUT = sys2x_clk_ecsout), Instance("ECLKSYNCB", - i_ECLKI = self.cd_sys2x_i.clk, + i_ECLKI = sys2x_clk_ecsout, i_STOP = self.stop, o_ECLKO = self.cd_sys2x.clk), Instance("CLKDIVF",