modules: update existsing SO-DIMM timings based on SPD data
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@ -571,48 +571,53 @@ class IS43TR16128B(SDRAMModule):
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# DDR3 (SO-DIMM) -----------------------------------------------------------------------------------
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class MT8JTF12864(SDRAMModule):
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# base chip: MT41J128M8
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80))
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
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speedgrade_timings = {
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 110), tFAW=(None, 37.5), tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 110), tFAW=(None, 30), tRAS=36),
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}
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speedgrade_timings["default"] = speedgrade_timings["1333"]
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class MT8KTF51264(SDRAMModule):
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# base chip: MT41K512M8
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80))
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
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speedgrade_timings = {
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"800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=(260, None), tFAW=(None, 50), tRAS=None),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None),
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"800" : _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 40), tRAS=37.5),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 40), tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=36),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35),
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"1866": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 27), tRAS=34),
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}
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speedgrade_timings["default"] = speedgrade_timings["1333"]
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speedgrade_timings["default"] = speedgrade_timings["1866"]
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class MT18KSF1G72HZ(SDRAMModule):
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# base chip: MT41K512M8
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80))
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
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speedgrade_timings = {
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=(128, None), tFAW=(None, 40), tRAS=None),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 40), tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=36),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35),
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}
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speedgrade_timings["default"] = speedgrade_timings["1600"]
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@ -632,20 +637,22 @@ class AS4C256M16D3A(SDRAMModule):
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class MT16KTF1G64HZ(SDRAMModule):
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# base chip: MT41K512M8
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80))
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
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speedgrade_timings = {
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"800" : _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(140, None), tFAW=(None, 40), tRAS=None),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(187, None), tFAW=(None, 40), tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(234, None), tFAW=(None, 30), tRAS=None),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=(280, None), tFAW=(None, 30), tRAS=None),
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"800" : _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 40), tRAS=37.5),
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 40), tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=36),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35),
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"1866": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 27), tRAS=34),
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}
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speedgrade_timings["default"] = speedgrade_timings["1600"]
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speedgrade_timings["default"] = speedgrade_timings["1866"]
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# DDR4 (Chips) -------------------------------------------------------------------------------------
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@ -1,76 +0,0 @@
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Part Number,Byte Number,Byte Description,Byte Value
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MT16KTF1G64HZ-1G6N1,0,DDR3-CRC RANGE; EEPROM BYTES; BYTES USED,92
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MT16KTF1G64HZ-1G6N1,1,DDR3-SPD REVISON,13
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MT16KTF1G64HZ-1G6N1,2,DDR3-DRAM DEVICE TYPE,0B
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MT16KTF1G64HZ-1G6N1,3,DDR3-MODULE TYPE (FORM FACTOR),03
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MT16KTF1G64HZ-1G6N1,4,DDR3-SDRAM DEVICE DENSITY BANKS,04
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MT16KTF1G64HZ-1G6N1,5,DDR3-SDRAM DEVICE ROW COLUMN COUNT,21
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MT16KTF1G64HZ-1G6N1,6,DDR3-MODULE NOMINAL VDD,02
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MT16KTF1G64HZ-1G6N1,7,DDR3-MODULE RANKS DEVICE DQ COUNT,09
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MT16KTF1G64HZ-1G6N1,8,DDR3-ECC TAG MODULE MEMORY BUS WIDTH,03
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MT16KTF1G64HZ-1G6N1,9,DDR3-FINE TIMEBASE DIVIDEND/DIVISOR,11
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MT16KTF1G64HZ-1G6N1,10,DDR3-MEDIUM TIMEBASE DIVIDEND,01
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MT16KTF1G64HZ-1G6N1,11,DDR3-MEDIUM TIMEBASE DIVISOR,08
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MT16KTF1G64HZ-1G6N1,12,DDR3-MIN SDRAM CYCLE TIME (TCKMIN),0A
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MT16KTF1G64HZ-1G6N1,13,DDR3-BYTE 13 RESERVED,00
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MT16KTF1G64HZ-1G6N1,14,DDR3-CAS LATENCIES SUPPORTED (CL4 => CL11),FE
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MT16KTF1G64HZ-1G6N1,15,DDR3-CAS LATENCIES SUPPORTED (CL12 => CL18),00
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MT16KTF1G64HZ-1G6N1,16,DDR3-MIN CAS LATENCY TIME (TAAMIN),69
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MT16KTF1G64HZ-1G6N1,17,DDR3-MIN WRITE RECOVERY TIME (TWRMIN),78
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MT16KTF1G64HZ-1G6N1,18,DDR3-MIN RAS# TO CAS# DELAY (TRCDMIN),69
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MT16KTF1G64HZ-1G6N1,19,DDR3-MIN ROW ACTIVE TO ROW ACTIVE DELAY (TRRDMIN),30
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MT16KTF1G64HZ-1G6N1,20,DDR3-MIN ROW PRECHARGE DELAY (TRPMIN),69
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MT16KTF1G64HZ-1G6N1,21,DDR3-UPPER NIBBLE FOR TRAS TRC,11
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MT16KTF1G64HZ-1G6N1,22,DDR3-MIN ACTIVE TO PRECHARGE DELAY (TRASMIN),18
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MT16KTF1G64HZ-1G6N1,23,DDR3-MIN ACTIVE TO ACTIVE/REFRESH DELAY (TRCMIN),81
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MT16KTF1G64HZ-1G6N1,24,DDR3-MIN REFRESH RECOVERY DELAY (TRFCMIN) LSB,20
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MT16KTF1G64HZ-1G6N1,25,DDR3-MIN REFRESH RECOVERY DELAY (TRFCMIN) MSB,08
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MT16KTF1G64HZ-1G6N1,26,DDR3-MIN INTERNAL WRITE TO READ CMD DELAY (TWTRMIN),3C
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MT16KTF1G64HZ-1G6N1,27,DDR3-MIN INTERNAL READ TO PRECHARGE CMD DELAY (TRTPMIN),3C
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MT16KTF1G64HZ-1G6N1,28,DDR3-MIN FOUR ACTIVE WINDOW DELAY (TFAWMIN) MSB,00
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MT16KTF1G64HZ-1G6N1,29,DDR3-MIN FOUR ACTIVE WINDOW DELAY (TFAWMIN) LSB,F0
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MT16KTF1G64HZ-1G6N1,30,DDR3-SDRAM DEVICE OUTPUT DRIVERS SUPPORTED,83
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MT16KTF1G64HZ-1G6N1,31,DDR3-SDRAM DEVICE THERMAL REFRESH OPTIONS,05
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MT16KTF1G64HZ-1G6N1,32,DDR3-MODULE THERMAL SENSOR,00
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MT16KTF1G64HZ-1G6N1,33,DDR3-SDRAM DEVICE TYPE,00
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MT16KTF1G64HZ-1G6N1,34,DDR3-FINE OFFSET FOR TCKMIN,00
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MT16KTF1G64HZ-1G6N1,35,DDR3-FINE OFFSET FOR TAAMIN,00
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MT16KTF1G64HZ-1G6N1,36,DDR3-FINE OFFSET FOR TRCDMIN,00
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MT16KTF1G64HZ-1G6N1,37,DDR3-FINE OFFSET FOR TRPMIN,00
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MT16KTF1G64HZ-1G6N1,38,DDR3-FINE OFFSET FOR TRCMIN,00
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MT16KTF1G64HZ-1G6N1,39,DDR3-BYTE 39 RESERVED,00
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MT16KTF1G64HZ-1G6N1,40,DDR3-BYTE 40 RESERVED,00
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MT16KTF1G64HZ-1G6N1,41,DDR3-PTRR TMAW MAC,88
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MT16KTF1G64HZ-1G6N1,42-59,DDR3-RESERVED BYTES 42-59,000000000000000000000000000000000000
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MT16KTF1G64HZ-1G6N1,60,DDR3-RC REV NOM MODULE HEIGHT,0F
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MT16KTF1G64HZ-1G6N1,61,DDR3-MODULE THICKNESS (MAX),11
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MT16KTF1G64HZ-1G6N1,62,DDR3-REFERENCE RAW CARD ID,65
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MT16KTF1G64HZ-1G6N1,63,DDR3 - ADDRESS MAPPING/MODULE ATTRIBUTES,00
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MT16KTF1G64HZ-1G6N1,64,DDR3-HEATSPREADER SOLUTION,00
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MT16KTF1G64HZ-1G6N1,65,DDR3-REGISTER VENDOR ID (LSB),00
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MT16KTF1G64HZ-1G6N1,66,DDR3-REGISTER VENDOR ID (MSB),00
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MT16KTF1G64HZ-1G6N1,67,DDR3-REGISTER REVISON NUMBER,00
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MT16KTF1G64HZ-1G6N1,68,DDR3-REGISTER TYPE,00
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MT16KTF1G64HZ-1G6N1,69,DDR3-REG CTRL WORDS 1 AND ZERO,00
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MT16KTF1G64HZ-1G6N1,70,DDR3-REG CTRL WORDS 3 AND 2,00
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MT16KTF1G64HZ-1G6N1,71,DDR3-REG CTRL WORDS 5 AND 4,00
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MT16KTF1G64HZ-1G6N1,72,DDR3-REG CTRL WORDS 7 AND 6,00
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MT16KTF1G64HZ-1G6N1,73,DDR3-REG CTRL WORDS 9 AND 8,00
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MT16KTF1G64HZ-1G6N1,74,DDR3-REG CTRL WORDS 11 AND 10,00
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MT16KTF1G64HZ-1G6N1,75,DDR3-REG CTRL WORDS 13 AND 12,00
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MT16KTF1G64HZ-1G6N1,76,DDR3-REG CTRL WORDS 15 AND 14,00
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MT16KTF1G64HZ-1G6N1,77-116,DDR3-RESERVED BYTES 77-116,00000000000000000000000000000000000000000000000000000000000000000000000000000000
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MT16KTF1G64HZ-1G6N1,117,DDR3-MODULE MFR ID (LSB),80
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MT16KTF1G64HZ-1G6N1,118,DDR3-MODULE MFR ID (MSB),2C
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MT16KTF1G64HZ-1G6N1,119,DDR3-MODULE MFR LOCATION ID,00
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MT16KTF1G64HZ-1G6N1,120,DDR3-MODULE MFR YEAR,00
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MT16KTF1G64HZ-1G6N1,121,DDR3-MODULE MFR WEEK,00
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MT16KTF1G64HZ-1G6N1,122-125,DDR3-MODULE SERIAL NUMBER,00000000
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MT16KTF1G64HZ-1G6N1,126-127,DDR3-CRC,5759
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MT16KTF1G64HZ-1G6N1,128-145,DDR3-MODULE PART NUMBER,16KTF1G64HZ-1G6N1
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MT16KTF1G64HZ-1G6N1,146,DDR3-MODULE DIE REV,4E
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MT16KTF1G64HZ-1G6N1,147,DDR3-MODULE PCB REV,31
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MT16KTF1G64HZ-1G6N1,148,DDR3-DRAM DEVICE MFR ID (LSB),80
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MT16KTF1G64HZ-1G6N1,149,DDR3-DRAM DEVICE MFR (MSB),2C
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MT16KTF1G64HZ-1G6N1,150-175,DDR3-MFR RESERVED BYTES 150-175,0000000000000000000000000000000000000000000000000000
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MT16KTF1G64HZ-1G6N1,176-255,DDR3-CUSTOMER RESERVED BYTES 176-255,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
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@ -0,0 +1,76 @@
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Part Number,Byte Number,Byte Description,Byte Value
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MT16KTF1G64HZ-1G6P1,0,DDR3-CRC RANGE; EEPROM BYTES; BYTES USED,92
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MT16KTF1G64HZ-1G6P1,1,DDR3-SPD REVISON,13
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MT16KTF1G64HZ-1G6P1,2,DDR3-DRAM DEVICE TYPE,0B
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MT16KTF1G64HZ-1G6P1,3,DDR3-MODULE TYPE (FORM FACTOR),03
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MT16KTF1G64HZ-1G6P1,4,DDR3-SDRAM DEVICE DENSITY BANKS,04
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MT16KTF1G64HZ-1G6P1,5,DDR3-SDRAM DEVICE ROW COLUMN COUNT,21
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MT16KTF1G64HZ-1G6P1,6,DDR3-MODULE NOMINAL VDD,02
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MT16KTF1G64HZ-1G6P1,7,DDR3-MODULE RANKS DEVICE DQ COUNT,09
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MT16KTF1G64HZ-1G6P1,8,DDR3-ECC TAG MODULE MEMORY BUS WIDTH,03
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MT16KTF1G64HZ-1G6P1,9,DDR3-FINE TIMEBASE DIVIDEND/DIVISOR,11
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MT16KTF1G64HZ-1G6P1,10,DDR3-MEDIUM TIMEBASE DIVIDEND,01
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MT16KTF1G64HZ-1G6P1,11,DDR3-MEDIUM TIMEBASE DIVISOR,08
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MT16KTF1G64HZ-1G6P1,12,DDR3-MIN SDRAM CYCLE TIME (TCKMIN),0A
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MT16KTF1G64HZ-1G6P1,13,DDR3-BYTE 13 RESERVED,00
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MT16KTF1G64HZ-1G6P1,14,DDR3-CAS LATENCIES SUPPORTED (CL4 => CL11),FE
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MT16KTF1G64HZ-1G6P1,15,DDR3-CAS LATENCIES SUPPORTED (CL12 => CL18),00
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MT16KTF1G64HZ-1G6P1,16,DDR3-MIN CAS LATENCY TIME (TAAMIN),69
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MT16KTF1G64HZ-1G6P1,17,DDR3-MIN WRITE RECOVERY TIME (TWRMIN),78
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MT16KTF1G64HZ-1G6P1,18,DDR3-MIN RAS# TO CAS# DELAY (TRCDMIN),69
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MT16KTF1G64HZ-1G6P1,19,DDR3-MIN ROW ACTIVE TO ROW ACTIVE DELAY (TRRDMIN),30
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MT16KTF1G64HZ-1G6P1,20,DDR3-MIN ROW PRECHARGE DELAY (TRPMIN),69
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MT16KTF1G64HZ-1G6P1,21,DDR3-UPPER NIBBLE FOR TRAS TRC,11
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MT16KTF1G64HZ-1G6P1,22,DDR3-MIN ACTIVE TO PRECHARGE DELAY (TRASMIN),18
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MT16KTF1G64HZ-1G6P1,23,DDR3-MIN ACTIVE TO ACTIVE/REFRESH DELAY (TRCMIN),81
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MT16KTF1G64HZ-1G6P1,24,DDR3-MIN REFRESH RECOVERY DELAY (TRFCMIN) LSB,20
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MT16KTF1G64HZ-1G6P1,25,DDR3-MIN REFRESH RECOVERY DELAY (TRFCMIN) MSB,08
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MT16KTF1G64HZ-1G6P1,26,DDR3-MIN INTERNAL WRITE TO READ CMD DELAY (TWTRMIN),3C
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MT16KTF1G64HZ-1G6P1,27,DDR3-MIN INTERNAL READ TO PRECHARGE CMD DELAY (TRTPMIN),3C
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MT16KTF1G64HZ-1G6P1,28,DDR3-MIN FOUR ACTIVE WINDOW DELAY (TFAWMIN) MSB,00
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MT16KTF1G64HZ-1G6P1,29,DDR3-MIN FOUR ACTIVE WINDOW DELAY (TFAWMIN) LSB,F0
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MT16KTF1G64HZ-1G6P1,30,DDR3-SDRAM DEVICE OUTPUT DRIVERS SUPPORTED,83
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MT16KTF1G64HZ-1G6P1,31,DDR3-SDRAM DEVICE THERMAL REFRESH OPTIONS,05
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MT16KTF1G64HZ-1G6P1,32,DDR3-MODULE THERMAL SENSOR,00
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MT16KTF1G64HZ-1G6P1,33,DDR3-SDRAM DEVICE TYPE,00
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MT16KTF1G64HZ-1G6P1,34,DDR3-FINE OFFSET FOR TCKMIN,00
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MT16KTF1G64HZ-1G6P1,35,DDR3-FINE OFFSET FOR TAAMIN,00
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MT16KTF1G64HZ-1G6P1,36,DDR3-FINE OFFSET FOR TRCDMIN,00
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MT16KTF1G64HZ-1G6P1,37,DDR3-FINE OFFSET FOR TRPMIN,00
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MT16KTF1G64HZ-1G6P1,38,DDR3-FINE OFFSET FOR TRCMIN,00
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MT16KTF1G64HZ-1G6P1,39,DDR3-BYTE 39 RESERVED,00
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||||
MT16KTF1G64HZ-1G6P1,40,DDR3-BYTE 40 RESERVED,00
|
||||
MT16KTF1G64HZ-1G6P1,41,DDR3-PTRR TMAW MAC,88
|
||||
MT16KTF1G64HZ-1G6P1,42-59,DDR3-RESERVED BYTES 42-59,000000000000000000000000000000000000
|
||||
MT16KTF1G64HZ-1G6P1,60,DDR3-RC REV NOM MODULE HEIGHT,0F
|
||||
MT16KTF1G64HZ-1G6P1,61,DDR3-MODULE THICKNESS (MAX),11
|
||||
MT16KTF1G64HZ-1G6P1,62,DDR3-REFERENCE RAW CARD ID,65
|
||||
MT16KTF1G64HZ-1G6P1,63,DDR3 - ADDRESS MAPPING/MODULE ATTRIBUTES,00
|
||||
MT16KTF1G64HZ-1G6P1,64,DDR3-HEATSPREADER SOLUTION,00
|
||||
MT16KTF1G64HZ-1G6P1,65,DDR3-REGISTER VENDOR ID (LSB),00
|
||||
MT16KTF1G64HZ-1G6P1,66,DDR3-REGISTER VENDOR ID (MSB),00
|
||||
MT16KTF1G64HZ-1G6P1,67,DDR3-REGISTER REVISON NUMBER,00
|
||||
MT16KTF1G64HZ-1G6P1,68,DDR3-REGISTER TYPE,00
|
||||
MT16KTF1G64HZ-1G6P1,69,DDR3-REG CTRL WORDS 1 AND ZERO,00
|
||||
MT16KTF1G64HZ-1G6P1,70,DDR3-REG CTRL WORDS 3 AND 2,00
|
||||
MT16KTF1G64HZ-1G6P1,71,DDR3-REG CTRL WORDS 5 AND 4,00
|
||||
MT16KTF1G64HZ-1G6P1,72,DDR3-REG CTRL WORDS 7 AND 6,00
|
||||
MT16KTF1G64HZ-1G6P1,73,DDR3-REG CTRL WORDS 9 AND 8,00
|
||||
MT16KTF1G64HZ-1G6P1,74,DDR3-REG CTRL WORDS 11 AND 10,00
|
||||
MT16KTF1G64HZ-1G6P1,75,DDR3-REG CTRL WORDS 13 AND 12,00
|
||||
MT16KTF1G64HZ-1G6P1,76,DDR3-REG CTRL WORDS 15 AND 14,00
|
||||
MT16KTF1G64HZ-1G6P1,77-116,DDR3-RESERVED BYTES 77-116,00000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
MT16KTF1G64HZ-1G6P1,117,DDR3-MODULE MFR ID (LSB),80
|
||||
MT16KTF1G64HZ-1G6P1,118,DDR3-MODULE MFR ID (MSB),2C
|
||||
MT16KTF1G64HZ-1G6P1,119,DDR3-MODULE MFR LOCATION ID,00
|
||||
MT16KTF1G64HZ-1G6P1,120,DDR3-MODULE MFR YEAR,00
|
||||
MT16KTF1G64HZ-1G6P1,121,DDR3-MODULE MFR WEEK,00
|
||||
MT16KTF1G64HZ-1G6P1,122-125,DDR3-MODULE SERIAL NUMBER,00000000
|
||||
MT16KTF1G64HZ-1G6P1,126-127,DDR3-CRC,5759
|
||||
MT16KTF1G64HZ-1G6P1,128-145,DDR3-MODULE PART NUMBER,16KTF1G64HZ-1G6P1
|
||||
MT16KTF1G64HZ-1G6P1,146,DDR3-MODULE DIE REV,50
|
||||
MT16KTF1G64HZ-1G6P1,147,DDR3-MODULE PCB REV,31
|
||||
MT16KTF1G64HZ-1G6P1,148,DDR3-DRAM DEVICE MFR ID (LSB),80
|
||||
MT16KTF1G64HZ-1G6P1,149,DDR3-DRAM DEVICE MFR (MSB),2C
|
||||
MT16KTF1G64HZ-1G6P1,150-175,DDR3-MFR RESERVED BYTES 150-175,0000000000000000000000000000000000000000000000000000
|
||||
MT16KTF1G64HZ-1G6P1,176-255,DDR3-CUSTOMER RESERVED BYTES 176-255,FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
|
|
@ -44,39 +44,47 @@ class TestSPD(unittest.TestCase):
|
|||
self.assertEqual(speedgrade, DDR3SPDData.speedgrade_freq(tck))
|
||||
|
||||
def compare_geometry(self, module, module_ref):
|
||||
self.assertEqual(module.memtype, module_ref.memtype)
|
||||
self.assertEqual(module.nbanks, module_ref.nbanks)
|
||||
self.assertEqual(module.nrows, module_ref.nrows)
|
||||
self.assertEqual(module.ncols, module_ref.ncols)
|
||||
|
||||
def compare_timings(self, module, module_ref):
|
||||
self.assertEqual(module.memtype, module_ref.memtype)
|
||||
|
||||
# technology timings
|
||||
compared_timings = ["tREFI", "tWTR", "tCCD", "tRRD", "tZQCS"]
|
||||
for timing in compared_timings:
|
||||
def compare_technology_timings(self, module, module_ref, omit=None):
|
||||
timings = {"tREFI", "tWTR", "tCCD", "tRRD", "tZQCS"}
|
||||
if omit is not None:
|
||||
timings -= omit
|
||||
for timing in timings:
|
||||
txx = getattr(module.technology_timings, timing)
|
||||
txx_ref = getattr(module_ref.technology_timings, timing)
|
||||
with self.subTest(txx="technology_timings:" + timing):
|
||||
with self.subTest(txx=timing):
|
||||
self.assertEqual(txx, txx_ref)
|
||||
|
||||
# speedgrade timings
|
||||
compared_timings = ["tRP", "tRCD", "tWR", "tRFC", "tFAW", "tRAS"]
|
||||
for freq, timings in module.speedgrade_timings.items():
|
||||
for timing in compared_timings:
|
||||
txx = getattr(timings, timing)
|
||||
def compare_speedgrade_timings(self, module, module_ref, omit=None):
|
||||
timings = {"tRP", "tRCD", "tWR", "tRFC", "tFAW", "tRAS"}
|
||||
if omit is not None:
|
||||
timings -= omit
|
||||
for freq, speedgrade_timings in module.speedgrade_timings.items():
|
||||
if freq == "default":
|
||||
continue
|
||||
for timing in timings:
|
||||
txx = getattr(speedgrade_timings, timing)
|
||||
txx_ref = getattr(module_ref.speedgrade_timings[freq], timing)
|
||||
with self.subTest(txx="speedgrade_timings:" + timing):
|
||||
with self.subTest(freq=freq, txx=timing):
|
||||
self.assertEqual(txx, txx_ref)
|
||||
|
||||
def compare_modules(self, module, module_ref, omit=None):
|
||||
self.assertEqual(module.memtype, module_ref.memtype)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_technology_timings(module, module_ref, omit=omit)
|
||||
self.compare_speedgrade_timings(module, module_ref, omit=omit)
|
||||
|
||||
def test_MT16KTF1G64HZ(self):
|
||||
kwargs = dict(clk_freq=125e6, rate="1:4")
|
||||
module_ref = litedram.modules.MT16KTF1G64HZ(**kwargs)
|
||||
|
||||
with self.subTest(speedgrade="-1G6"):
|
||||
data = load_spd_reference("MT16KTF1G64HZ-1G6N1.csv")
|
||||
data = load_spd_reference("MT16KTF1G64HZ-1G6P1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1600"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -85,7 +93,9 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G9"):
|
||||
data = load_spd_reference("MT16KTF1G64HZ-1G9E1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
# tRRD it different for this speedgrade
|
||||
self.compare_modules(module, module_ref, omit={"tRRD"})
|
||||
self.assertEqual(module.technology_timings.tRRD, (4, 5))
|
||||
sgt = module.speedgrade_timings["1866"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -98,7 +108,7 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G6"):
|
||||
data = load_spd_reference("MT18KSF1G72HZ-1G6E2.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1600"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -107,7 +117,7 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G4"):
|
||||
data = load_spd_reference("MT18KSF1G72HZ-1G4E2.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1333"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -119,7 +129,7 @@ class TestSPD(unittest.TestCase):
|
|||
|
||||
data = load_spd_reference("MT8JTF12864AZ-1G4G1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1333"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -132,7 +142,7 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G4"):
|
||||
data = load_spd_reference("MT8KTF51264HZ-1G4E1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1333"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -141,7 +151,7 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G6"):
|
||||
data = load_spd_reference("MT8KTF51264HZ-1G6E1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
self.compare_modules(module, module_ref)
|
||||
sgt = module.speedgrade_timings["1600"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
@ -150,7 +160,9 @@ class TestSPD(unittest.TestCase):
|
|||
with self.subTest(speedgrade="-1G9"):
|
||||
data = load_spd_reference("MT8KTF51264HZ-1G9P1.csv")
|
||||
module = SDRAMModule.from_spd_data(data, **kwargs)
|
||||
self.compare_geometry(module, module_ref)
|
||||
# tRRD different for this timing
|
||||
self.compare_modules(module, module_ref, omit={"tRRD"})
|
||||
self.assertEqual(module.technology_timings.tRRD, (4, 5))
|
||||
sgt = module.speedgrade_timings["1866"]
|
||||
self.assertEqual(sgt.tRP, 13.125)
|
||||
self.assertEqual(sgt.tRCD, 13.125)
|
||||
|
|
Loading…
Reference in New Issue