From 0ac23fde52cbe365924a064b52772234dd0f5e8b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Oct 2020 18:08:36 +0200
Subject: [PATCH] phy/s7ddrphy: increase write_latency by 1 (now possible with
 previous BitSlip chantges).

---
 litedram/phy/s7ddrphy.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index 88b143e..b4d4619 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -98,7 +98,7 @@ class S7DDRPHY(Module, AutoCSR):
             cl            = cl,
             cwl           = cwl,
             read_latency  = cl_sys_latency + 6,
-            write_latency = cwl_sys_latency - 2,
+            write_latency = cwl_sys_latency - 1,
             cmd_latency   = cmd_latency,
             cmd_delay     = cmd_delay,
         )