diff --git a/test/reference/__init__.py b/test/reference/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h new file mode 100644 index 0000000..d1c7d66 --- /dev/null +++ b/test/reference/ddr3_init.h @@ -0,0 +1,100 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +__attribute__((unused)) static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +__attribute__((unused)) static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +__attribute__((unused)) static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X) +#define command_prd(X) command_p1(X) +#define command_pwr(X) command_p2(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDRX_MR1 6 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 2, CWL=6 */ + sdram_dfii_pi0_address_write(0x208); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x6); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=7, BL=8 */ + sdram_dfii_pi0_address_write(0x930); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/reference/ddr3_init.py b/test/reference/ddr3_init.py new file mode 100644 index 0000000..d1c7d66 --- /dev/null +++ b/test/reference/ddr3_init.py @@ -0,0 +1,100 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +__attribute__((unused)) static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +__attribute__((unused)) static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +__attribute__((unused)) static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X) +#define command_prd(X) command_p1(X) +#define command_pwr(X) command_p2(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDRX_MR1 6 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 2, CWL=6 */ + sdram_dfii_pi0_address_write(0x208); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x6); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=7, BL=8 */ + sdram_dfii_pi0_address_write(0x930); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h new file mode 100644 index 0000000..c970d97 --- /dev/null +++ b/test/reference/ddr4_init.h @@ -0,0 +1,115 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +__attribute__((unused)) static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +__attribute__((unused)) static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +__attribute__((unused)) static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi3_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi3_baddress_write(X) +#define command_prd(X) command_p1(X) +#define command_pwr(X) command_p3(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDRX_MR1 769 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 6 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(6); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 5 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(5); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 4 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(4); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 2, CWL=9 */ + sdram_dfii_pi0_address_write(0x200); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x301); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=11, BL=8 */ + sdram_dfii_pi0_address_write(0x110); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/reference/ddr4_init.py b/test/reference/ddr4_init.py new file mode 100644 index 0000000..c970d97 --- /dev/null +++ b/test/reference/ddr4_init.py @@ -0,0 +1,115 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +__attribute__((unused)) static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +__attribute__((unused)) static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +__attribute__((unused)) static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi3_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi3_baddress_write(X) +#define command_prd(X) command_p1(X) +#define command_pwr(X) command_p3(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDRX_MR1 769 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 6 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(6); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 5 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(5); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 4 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(4); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 2, CWL=9 */ + sdram_dfii_pi0_address_write(0x200); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x301); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=11, BL=8 */ + sdram_dfii_pi0_address_write(0x110); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h new file mode 100644 index 0000000..9337aec --- /dev/null +++ b/test/reference/sdr_init.h @@ -0,0 +1,78 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 1 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define command_prd(X) command_p0(X) +#define command_pwr(X) command_p0(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[1] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[1] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR +}; + +static void init_sequence(void) +{ + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(20000); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register / Reset DLL, CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x120); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Load Mode Register / CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x20); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/reference/sdr_init.py b/test/reference/sdr_init.py new file mode 100644 index 0000000..9337aec --- /dev/null +++ b/test/reference/sdr_init.py @@ -0,0 +1,78 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 1 + +static void cdelay(int i); + +__attribute__((unused)) static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define command_prd(X) command_p0(X) +#define command_pwr(X) command_p0(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned long sdram_dfii_pix_wrdata_addr[1] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR +}; + +const unsigned long sdram_dfii_pix_rddata_addr[1] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR +}; + +static void init_sequence(void) +{ + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(20000); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register / Reset DLL, CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x120); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Load Mode Register / CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x20); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/test/test_init.py b/test/test_init.py new file mode 100644 index 0000000..692df7e --- /dev/null +++ b/test/test_init.py @@ -0,0 +1,41 @@ +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + +import os +import filecmp +import unittest + +from litex.build.tools import write_to_file + +from litedram.init import get_sdram_phy_c_header, get_sdram_phy_py_header + + +def compare_with_reference(content, filename): + write_to_file(filename, content) + return filecmp.cmp(filename, os.path.join("test", "reference", filename)) + + +class TestInit(unittest.TestCase): + def test_sdr(self): + from litex.boards.targets.minispartan6 import BaseSoC + soc = BaseSoC() + c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True) + self.assertEqual(compare_with_reference(c_header, "sdr_init.py"), True) + + def test_ddr3(self): + from litex.boards.targets.kc705 import BaseSoC + soc = BaseSoC() + c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True) + self.assertEqual(compare_with_reference(c_header, "ddr3_init.py"), True) + + def test_ddr4(self): + from litex.boards.targets.kcu105 import BaseSoC + soc = BaseSoC() + c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) + self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True) + self.assertEqual(compare_with_reference(c_header, "ddr4_init.py"), True)