diff --git a/litedram/common.py b/litedram/common.py
index 18fc903..9a4ed42 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -10,8 +10,7 @@ class PhySettings:
                  nphases,
                  rdphase, wrphase,
                  rdcmdphase, wrcmdphase,
-                 cl, read_latency, write_latency, cwl=0,
-                 rtt_nom='40ohm', drive_strength='40ohm', dynamic_odt='60ohm'):
+                 cl, read_latency, write_latency, cwl=None):
         self.memtype = memtype
         self.dfi_databits = dfi_databits
 
@@ -26,10 +25,12 @@ class PhySettings:
         self.write_latency = write_latency
         self.cwl = cwl
 
-        # board tuning parameters
-        self.rtt_nom = rtt_nom
-        self.drive_strength = drive_strength
-        self.dynamic_odt = dynamic_odt
+    # Optional DDR3 electrical settings
+    def add_electrical_settings(rtt_nom, rtt_wr, ron):
+        assert self.memtype == "DDR3"
+        self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance
+        self.rtt_wr = rtt_wr   # Writes on-die termination impedance
+        self.ron = ron         # Output driver impedance
 
 
 class GeomSettings:
diff --git a/litedram/sdram_init.py b/litedram/sdram_init.py
index 6f04ab9..3789191 100644
--- a/litedram/sdram_init.py
+++ b/litedram/sdram_init.py
@@ -175,9 +175,9 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
             mr0 |= wr_to_mr0[wr] << 9
             return mr0
 
-        def format_mr1(output_drive_strength, rtt_nom):
-            mr1 = ((output_drive_strength >> 0) & 1) << 1
-            mr1 |= ((output_drive_strength >> 1) & 1) << 5
+        def format_mr1(ron, rtt_nom):
+            mr1 = ((ron >> 0) & 1) << 1
+            mr1 |= ((ron >> 1) & 1) << 5
             mr1 |= ((rtt_nom >> 0) & 1) << 2
             mr1 |= ((rtt_nom >> 1) & 1) << 6
             mr1 |= ((rtt_nom >> 2) & 1) << 9
@@ -188,26 +188,46 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
             mr2 |= rtt_wr << 9
             return mr2
 
-        z_to_rttnom = {
-            'disabled' : 0,
-            '60ohm'    : 1,
-            '120ohm'   : 2,
-            '40ohm'    : 3,
-            '20ohm'    : 4,
-            '30ohm'    : 5
+        z_to_rtt_nom = {
+            "disabled" : 0,
+            "60ohm"    : 1,
+            "120ohm"   : 2,
+            "40ohm"    : 3,
+            "20ohm"    : 4,
+            "30ohm"    : 5
         }
-        z_to_output_drive_strength = {
-            '40ohm' : 0,
-            '34ohm' : 1,
+
+        z_to_rtt_wr = {
+            "disabled" : 0,
+            "60ohm"    : 1,
+            "120ohm"   : 2,
         }
-        z_to_dynamic_odt = {
-            'disabled' : 0,
-            '60ohm'    : 1,
-            '120ohm'   : 2,
+
+        z_to_ron = {
+            "40ohm" : 0,
+            "34ohm" : 1,
         }
+
+        # default electrical settings (point to point)
+        rtt_nom = "60ohm"
+        rtt_wr = "120ohm"
+        ron = "34ohm"
+
+        # override electrical settings if specified
+        if hasattr(sdram_phy_settings, "rtt_nom"):
+            rtt_nom = sdram_phy_settings.rtt_nom
+        if hasattr(sdram_phy_settings, "rtt_wr"):
+            rtt_wr = sdram_phy_settings.rtt_wr
+        if hasattr(sdram_phy_settings, "ron"):
+            ron = sdram_phy_settings.ron
+
         mr0 = format_mr0(bl, cl, 14, 1)  # wr=8 FIXME: this should be ceiling(tWR/tCK)
-        mr1 = format_mr1(z_to_output_drive_strength[sdram_phy_settings.drive_strength], z_to_rttnom[sdram_phy_settings.rtt_nom])
-        mr2 = format_mr2(sdram_phy_settings.cwl, z_to_dynamic_odt[sdram_phy_settings.dynamic_odt])
+        mr1 = format_mr1(
+            z_to_ron[ron],
+            z_to_rtt_nom[rtt_nom])
+        mr2 = format_mr2(
+            sdram_phy_settings.cwl,
+            z_to_rtt_wr[rtt_wr])
         mr3 = 0
 
         init_sequence = [