From 0bb3bff8af782d186d453fbb54ac26d8d4e4a583 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Oct 2021 15:05:56 +0200 Subject: [PATCH] litedram_gen: Set default csr_data_width to 32 (similar to LiteX). --- litedram/gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index e1bcb58..8ccf36d 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -477,7 +477,7 @@ class LiteDRAMCore(SoCCore): sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] cpu_variant = core_config.get("cpu_variant", "standard") - csr_data_width = core_config.get("csr_data_width", 8) + csr_data_width = core_config.get("csr_data_width", 32) uart_type = core_config.get("uart", "rs232") if cpu_type is None: kwargs["integrated_rom_size"] = 0