From 0ecb1340f5b3d3341b460cfa389325b919e76619 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Tue, 16 Mar 2021 13:31:16 +0100
Subject: [PATCH] lpddr4/test: fixes: use 2tCK write preamble, update read
 latency

---
 litedram/phy/lpddr4/sim.py |  3 ++-
 test/test_lpddr4.py        | 44 +++++++++++++++++++++++++-------------
 2 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/litedram/phy/lpddr4/sim.py b/litedram/phy/lpddr4/sim.py
index edaccde..14317c2 100644
--- a/litedram/phy/lpddr4/sim.py
+++ b/litedram/phy/lpddr4/sim.py
@@ -530,9 +530,10 @@ class DataSim(Module, AutoCSR):
         write = Signal()
         read = Signal()
 
+        read_skew = 1  # shift the read data as in hardware it will be coming with a delay
         self.comb += [
             write.eq(cmds_sim.data_en.taps[cwl-1] & cmds_sim.data.source.valid & cmds_sim.data.source.we),
-            read.eq(cmds_sim.data_en.taps[cl-1] & cmds_sim.data.source.valid & ~cmds_sim.data.source.we),
+            read.eq(cmds_sim.data_en.taps[cl-1 + read_skew] & cmds_sim.data.source.valid & ~cmds_sim.data.source.we),
             cmds_sim.data.source.ready.eq(write | read),
             self.dq_wr.masked.eq(write & cmds_sim.data.source.masked),
             self.dq_wr.trigger.eq(write),
diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py
index 0dcb347..2676743 100644
--- a/test/test_lpddr4.py
+++ b/test/test_lpddr4.py
@@ -633,8 +633,8 @@ class LPDDR4Tests(unittest.TestCase):
                     'dq1':  (self.CMD_LATENCY+1)*zero + '00000000'+'00000000' + '11111111'+'11111111' + '00000000'+'00000000' + zero,
                 },
                 "sys8x_ddr": {  # preamble, pattern, preamble
-                    'dqs0': (self.CMD_LATENCY+1)*zero + '01010101'+'01010100' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
-                    'dqs1': (self.CMD_LATENCY+1)*zero + '01010101'+'01010100' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
+                    'dqs0': (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
+                    'dqs1': (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
                 }
             },
         )
@@ -671,7 +671,7 @@ class LPDDR4Tests(unittest.TestCase):
 
     def test_lpddr4_dq_in_rddata_valid(self):
         # Test that rddata_valid is set with correct delay
-        read_latency = 8  # settings.read_latency
+        read_latency = 9  # settings.read_latency
         dfi_sequence = [
             {0: dict(rddata_en=1)},  # command is issued by MC (appears on next cycle)
             *[{p: dict(rddata_valid=0) for p in range(8)} for _ in range(read_latency - 1)],  # nothing is sent during write latency
@@ -775,7 +775,7 @@ class LPDDR4Tests(unittest.TestCase):
                             for i in range(16)
                         },
                         "sys8x_ddr": {
-                            "dqs0": (self.CMD_LATENCY+1)*zero + '01010101'+'01010100' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
+                            "dqs0": (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
                         },
                     },
                 )
@@ -787,21 +787,35 @@ class LPDDR4Tests(unittest.TestCase):
         read_latency = phy.settings.read_latency
         rdphase = phy.settings.rdphase.reset.value
 
+        # FIXME: The data will appear 1 cycle before rddata_valid. This is because we have one more cycle
+        # of read latency that is needed for bitslips to be usable, and here we're not doing read leveling
+        # so the bitslip is configured incorrectly. If we increased cl by 1 in Simulator and did a single
+        # bitslip increment before the test, it should work, but this would unnecessarily complicate the test.
         dfi_data = {
-            0: dict(rddata=0x11112222, rddata_valid=1),
-            1: dict(rddata=0x33334444, rddata_valid=1),
-            2: dict(rddata=0x55556666, rddata_valid=1),
-            3: dict(rddata=0x77778888, rddata_valid=1),
-            4: dict(rddata=0x9999aaaa, rddata_valid=1),
-            5: dict(rddata=0xbbbbcccc, rddata_valid=1),
-            6: dict(rddata=0xddddeeee, rddata_valid=1),
-            7: dict(rddata=0xffff0000, rddata_valid=1),
+            0: dict(rddata=0x11112222),
+            1: dict(rddata=0x33334444),
+            2: dict(rddata=0x55556666),
+            3: dict(rddata=0x77778888),
+            4: dict(rddata=0x9999aaaa),
+            5: dict(rddata=0xbbbbcccc),
+            6: dict(rddata=0xddddeeee),
+            7: dict(rddata=0xffff0000),
+        }
+        dfi_data_valid = {
+            0: dict(rddata_valid=1),
+            1: dict(rddata_valid=1),
+            2: dict(rddata_valid=1),
+            3: dict(rddata_valid=1),
+            4: dict(rddata_valid=1),
+            5: dict(rddata_valid=1),
+            6: dict(rddata_valid=1),
+            7: dict(rddata_valid=1),
         }
         dfi_sequence = [
             {rdphase: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, rddata_en=1)},
-            *[{} for _ in range(read_latency - 1)],
+            *[{} for _ in range(read_latency - 1 - 1)],
             dfi_data,
-            {},
+            dfi_data_valid,
             {},
             {},
             {},
@@ -948,7 +962,7 @@ class LPDDR4Tests(unittest.TestCase):
                     for i in range(16)
                 },
                 "sys8x_ddr": {
-                    "dqs0": init_ddr_latency + '01010101'+'01010100' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
+                    "dqs0": init_ddr_latency + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
                 },
             },
         )