From 0f151c5499578e053987ec2f4e67f6e16bf69336 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 17 Dec 2016 19:22:56 +0100 Subject: [PATCH] frontend/bist: small cleanup --- litedram/frontend/bist.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index 3ea3dc8..89b8fdf 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -72,6 +72,7 @@ class Counter(Module): self.sync += self.o.eq(self.o + 1) +@ResetInserter() class _LiteDRAMBISTGenerator(Module): def __init__(self, dram_port, random): @@ -144,7 +145,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): cd = dram_port.cd - core = ResetInserter()(_LiteDRAMBISTGenerator(dram_port, random)) + core = _LiteDRAMBISTGenerator(dram_port, random) self.submodules.core = ClockDomainsRenamer(cd)(core) reset_sync = PulseSynchronizer("sys", cd) @@ -177,6 +178,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): ] +@ResetInserter() class _LiteDRAMBISTChecker(Module, AutoCSR): def __init__(self, dram_port, random): @@ -285,7 +287,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR): cd = dram_port.cd - core = ResetInserter()(_LiteDRAMBISTChecker(dram_port, random)) + core = _LiteDRAMBISTChecker(dram_port, random) self.submodules.core = ClockDomainsRenamer(cd)(core) reset_sync = PulseSynchronizer("sys", cd)