From 0f46dc4ab7706ba6089010e86dea13350bfaa68c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Oct 2018 11:59:54 +0200 Subject: [PATCH] modules: add DDR3-800 timings for MT41J128M16 and use it on arty example --- examples/arty_config.py | 2 +- litedram/modules.py | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/examples/arty_config.py b/examples/arty_config.py index 20bca1c..8ed4b75 100644 --- a/examples/arty_config.py +++ b/examples/arty_config.py @@ -8,7 +8,7 @@ core_config = { # modules / phy "sdram_module": MT41K128M16, "sdram_module_nb": 1, - "sdram_module_speedgrade": "1066", + "sdram_module_speedgrade": "800", "sdram_rank_nb": 1, "sdram_phy": A7DDRPHY, diff --git a/litedram/modules.py b/litedram/modules.py index da6a020..3964108 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -248,6 +248,14 @@ class MT41J128M16(SDRAMModule): tCCD = (4, None) tRRD = 10 # speedgrade related timings + # DDR3-800 + tRP_800 = 13.1 + tRCD_800 = 13.1 + tWR_800 = 13.1 + tRFC_800 = 64 + tFAW_800 = (20, None) + tRC_800 = 50.625 + tRAS_800 = 37.5 # DDR3-1066 tRP_1066 = 13.1 tRCD_1066 = 13.1