diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index f399bed..6a1a209 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -21,9 +21,9 @@
 #define SDRAM_PHY_PHASES 4
 #define SDRAM_PHY_CL 7
 #define SDRAM_PHY_CWL 6
-#define SDRAM_PHY_CMD_LATENCY 1
-#define SDRAM_PHY_RDPHASE 0
-#define SDRAM_PHY_WRPHASE 1
+#define SDRAM_PHY_CMD_LATENCY 0
+#define SDRAM_PHY_RDPHASE 1
+#define SDRAM_PHY_WRPHASE 2
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
 #define SDRAM_PHY_READ_LEVELING_CAPABLE
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index 5674de9..54391d0 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -21,9 +21,9 @@
 #define SDRAM_PHY_PHASES 4
 #define SDRAM_PHY_CL 9
 #define SDRAM_PHY_CWL 9
-#define SDRAM_PHY_CMD_LATENCY 1
-#define SDRAM_PHY_RDPHASE 2
-#define SDRAM_PHY_WRPHASE 2
+#define SDRAM_PHY_CMD_LATENCY 0
+#define SDRAM_PHY_RDPHASE 3
+#define SDRAM_PHY_WRPHASE 3
 #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
 #define SDRAM_PHY_WRITE_LEVELING_REINIT
 #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE