From 103534d0e82cf282bc15c7fa040a2a47acf4bf76 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 22 Apr 2021 18:34:18 +0200
Subject: [PATCH] init: Enable DQ-DQS training on 7-Series (except Artix7) and
 Ultrascale.

---
 litedram/init.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/litedram/init.py b/litedram/init.py
index 2cec01a..4adebca 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -689,13 +689,12 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
                    "K7DDRPHY", "V7DDRPHY",
                    "K7LPDDR4PHY", "V7LPDDR4PHY"]:
         r += "#define SDRAM_PHY_WRITE_LEVELING_CAPABLE\n"
+        r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
     if phytype in ["USDDRPHY", "USPDDRPHY",
                    "A7DDRPHY", "K7DDRPHY", "V7DDRPHY",
                    "A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
         r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
-    if phytype in ["K7LPDDR4PHY", "V7LPDDR4PHY"]:
-        r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
     if phytype in ["ECP5DDRPHY"]:
         r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
     if phytype in ["LPDDR4SIMPHY"]: