From 13cdbc0ed9c7194e93890eb6de2a004b43b2ad75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 1 Jun 2021 13:23:48 +0200 Subject: [PATCH] phy/utils: ConstBitSlip: allow for different bitrate relation of CA vs CS --- litedram/phy/utils.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litedram/phy/utils.py b/litedram/phy/utils.py index 22215cc..3454af3 100644 --- a/litedram/phy/utils.py +++ b/litedram/phy/utils.py @@ -201,6 +201,9 @@ class CommandsPipeline(Module): # Number of phases (before the current one) we need to check for overlaps n_previous = cmd_nphases_span - 1 + # Number of bits to slip CA per phase (how many CA output bits are equivalent to 1 CS output bit) + assert ca_ser_width % cs_ser_width == 0, f"Non-integer CA:CS output width ratio: {ca_ser_width % cs_ser_width}" + ca_phase_slip = ca_ser_width // cs_ser_width # Create a history of valid adapters used for masking overlapping ones valids = ConstBitSlip(dw=nphases, slp=0, cycles=1, register=False) @@ -230,7 +233,7 @@ class CommandsPipeline(Module): # For CA we need to do the same for each bit ca_bits = [] for bit in range(ca_nbits): - ca_bs = ConstBitSlip(dw=ca_ser_width, slp=phase, cycles=1) + ca_bs = ConstBitSlip(dw=ca_ser_width, slp=phase*ca_phase_slip, cycles=1) self.submodules += ca_bs ca_bit_hist = [ca[bit] for ca in adapter.ca] ca_mask = Replicate(allowed, len(ca_bs.o))