diff --git a/litedram/modules.py b/litedram/modules.py
index 7115698..a83c73c 100755
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -678,6 +678,18 @@ class MT41J256M8(DDR3Module):
     }
     speedgrade_timings["default"] = speedgrade_timings["1333"]
 
+class MT41K256M8(DDR3Module):
+    # geometry
+    nbanks = 8
+    nrows  = 32768
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
+    speedgrade_timings = {
+          "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(128, None), tFAW=(None, 40), tRAS=35),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["1600"]
+
 class MT41J128M16(DDR3Module):
     # geometry
     nbanks = 8