From 15f7ba27138367f21832e5c00e7882db8a6fab54 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 Apr 2022 11:46:43 +0200 Subject: [PATCH] frontend/adapter: Set with_common_rst to False on ClockDomainCrossing. --- litedram/frontend/adapter.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litedram/frontend/adapter.py b/litedram/frontend/adapter.py index 5928e83..5c1461e 100644 --- a/litedram/frontend/adapter.py +++ b/litedram/frontend/adapter.py @@ -32,7 +32,8 @@ class LiteDRAMNativePortCDC(Module): layout = [("we", 1), ("addr", address_width)], cd_from = port_from.clock_domain, cd_to = port_to.clock_domain, - depth = cmd_depth) + depth = cmd_depth, + with_common_rst = False) self.submodules += cmd_cdc self.submodules += stream.Pipeline(port_from.cmd, cmd_cdc, port_to.cmd) @@ -41,7 +42,8 @@ class LiteDRAMNativePortCDC(Module): layout = [("data", data_width), ("we", data_width//8)], cd_from = port_from.clock_domain, cd_to = port_to.clock_domain, - depth = wdata_depth) + depth = wdata_depth, + with_common_rst = False) self.submodules += wdata_cdc self.submodules += stream.Pipeline(port_from.wdata, wdata_cdc, port_to.wdata) @@ -50,7 +52,8 @@ class LiteDRAMNativePortCDC(Module): layout = [("data", data_width)], cd_from = port_to.clock_domain, cd_to = port_from.clock_domain, - depth = rdata_depth) + depth = rdata_depth, + with_common_rst = False) self.submodules += rdata_cdc self.submodules += stream.Pipeline(port_to.rdata, rdata_cdc, port_from.rdata)