From 16480d9aed87db71ef4e95630a1b945753a3bc8d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 2 Oct 2020 12:15:32 +0200
Subject: [PATCH] phy/s7ddrphy: adjust dqs/dq tristate latency.

OSERDESE2 has a latency of 2 sys_clk.
---
 litedram/phy/s7ddrphy.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index b492959..a4ca437 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -206,7 +206,7 @@ class S7DDRPHY(Module, AutoCSR):
         dqs_oe        = Signal()
         dqs_preamble  = Signal()
         dqs_postamble = Signal()
-        dqs_oe_delay  = TappedDelayLine(ntaps=1)
+        dqs_oe_delay  = TappedDelayLine(ntaps=2)
         dqs_pattern   = DQSPattern(
             preamble      = dqs_preamble,
             postamble     = dqs_postamble,
@@ -298,7 +298,7 @@ class S7DDRPHY(Module, AutoCSR):
 
         # DQ ---------------------------------------------------------------------------------------
         dq_oe = Signal()
-        dq_oe_delay = TappedDelayLine(ntaps=1)
+        dq_oe_delay = TappedDelayLine(ntaps=2)
         self.submodules += dq_oe_delay
         self.comb += dq_oe_delay.input.eq(dqs_preamble | dq_oe | dqs_postamble)
         for i in range(databits):