From 167c0c91f692f34dda9f8583aaabe52503194eb2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 11 Oct 2018 19:40:31 +0200 Subject: [PATCH] remove partial reordering code in master, keep things in bank_reordering branch. we'll try to stabilize master without reordering, then do some refactoring/adding a test suite to ease adding proper reordering later --- litedram/common.py | 21 ++++++--------------- litedram/core/controller.py | 4 +--- litedram/frontend/crossbar.py | 32 +++++++------------------------- litedram/frontend/dma.py | 2 +- litedram/frontend/ecc.py | 4 ++-- 5 files changed, 17 insertions(+), 46 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index 0f2cf2a..166a098 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -2,9 +2,6 @@ from migen import * from litex.soc.interconnect import stream -bankbits_max = 3 - - class PhySettings: def __init__(self, memtype, dfi_databits, nphases, @@ -77,9 +74,7 @@ def data_layout(data_width): return [ ("wdata", data_width, DIR_M_TO_S), ("wdata_we", data_width//8, DIR_M_TO_S), - ("wbank", bankbits_max, DIR_S_TO_M), - ("rdata", data_width, DIR_S_TO_M), - ("rbank", bankbits_max, DIR_S_TO_M) + ("rdata", data_width, DIR_S_TO_M) ] @@ -103,24 +98,20 @@ def cmd_description(address_width): ] -def wdata_description(data_width, with_bank): +def wdata_description(data_width): r = [ ("data", data_width), ("we", data_width//8) ] - if with_bank: - r += [("bank", bankbits_max)] return r -def rdata_description(data_width, with_bank): +def rdata_description(data_width): r = [("data", data_width)] - if with_bank: - r += [("bank", bankbits_max)] return r class LiteDRAMNativePort: - def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0, with_bank=False): + def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0): self.mode = mode self.address_width = address_width self.data_width = data_width @@ -130,8 +121,8 @@ class LiteDRAMNativePort: self.lock = Signal() self.cmd = stream.Endpoint(cmd_description(address_width)) - self.wdata = stream.Endpoint(wdata_description(data_width, with_bank)) - self.rdata = stream.Endpoint(rdata_description(data_width, with_bank)) + self.wdata = stream.Endpoint(wdata_description(data_width)) + self.rdata = stream.Endpoint(rdata_description(data_width)) self.flush = Signal() diff --git a/litedram/core/controller.py b/litedram/core/controller.py index f56b526..fe2087d 100644 --- a/litedram/core/controller.py +++ b/litedram/core/controller.py @@ -13,8 +13,7 @@ class ControllerSettings: read_time=32, write_time=16, with_bandwidth=False, with_refresh=True, - with_auto_precharge=True, - with_reordering=False): + with_auto_precharge=True): self.cmd_buffer_depth = cmd_buffer_depth self.cmd_buffer_buffered = cmd_buffer_buffered self.read_time = read_time @@ -22,7 +21,6 @@ class ControllerSettings: self.with_bandwidth = with_bandwidth self.with_refresh = with_refresh self.with_auto_precharge = with_auto_precharge - self.with_reordering = with_reordering class LiteDRAMController(Module): diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index fec6dcd..7f87618 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -49,8 +49,7 @@ class LiteDRAMCrossbar(Module): address_width=self.rca_bits + self.bank_bits - self.rank_bits, data_width=self.controller.data_width, clock_domain="sys", - id=len(self.masters), - with_bank=self.controller.settings.with_reordering) + id=len(self.masters)) self.masters.append(port) # clock domain crossing @@ -60,8 +59,7 @@ class LiteDRAMCrossbar(Module): address_width=port.address_width, data_width=port.data_width, clock_domain=clock_domain, - id=port.id, - with_bank=self.controller.settings.with_reordering) + id=port.id) self.submodules += LiteDRAMNativePortCDC(new_port, port) port = new_port @@ -76,8 +74,7 @@ class LiteDRAMCrossbar(Module): address_width=port.address_width + addr_shift, data_width=data_width, clock_domain=clock_domain, - id=port.id, - with_bank=self.controller.settings.with_reordering) + id=port.id) self.submodules += ClockDomainsRenamer(clock_domain)(LiteDRAMNativePortConverter(new_port, port, reverse)) port = new_port @@ -107,11 +104,10 @@ class LiteDRAMCrossbar(Module): master_locked = [] for nm, master in enumerate(self.masters): locked = Signal() - if not self.controller.settings.with_reordering: - for other_nb, other_arbiter in enumerate(arbiters): - if other_nb != nb: - other_bank = getattr(controller, "bank"+str(other_nb)) - locked = locked | (other_bank.lock & (other_arbiter.grant == nm)) + for other_nb, other_arbiter in enumerate(arbiters): + if other_nb != nb: + other_bank = getattr(controller, "bank"+str(other_nb)) + locked = locked | (other_bank.lock & (other_arbiter.grant == nm)) master_locked.append(locked) # arbitrate @@ -158,17 +154,6 @@ class LiteDRAMCrossbar(Module): master_rdata_valid = new_master_rdata_valid master_rdata_valids[nm] = master_rdata_valid - # Delay bank output to match rvalid - for i in range(self.read_latency-1): - new_master_rbank = Signal(max=self.nbanks) - self.sync += new_master_rbank.eq(rbank) - rbank = new_master_rbank - # Delay wbank output to match wready - for i in range(self.write_latency-1): - new_master_wbank = Signal(max=self.nbanks) - self.sync += new_master_wbank.eq(wbank) - wbank = new_master_wbank - for master, master_ready in zip(self.masters, master_readys): self.comb += master.cmd.ready.eq(master_ready) for master, master_wdata_ready in zip(self.masters, master_wdata_readys): @@ -192,9 +177,6 @@ class LiteDRAMCrossbar(Module): # route data reads for master in self.masters: self.comb += master.rdata.data.eq(self.controller.rdata) - if hasattr(master.rdata, "bank"): - self.comb += master.rdata.bank.eq(rbank) - self.comb += master.wdata.bank.eq(wbank) def split_master_addresses(self, bank_bits, rca_bits, cba_shift): m_ba = [] # bank address diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index bba640d..e89f9a1 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -83,7 +83,7 @@ class LiteDRAMDMAReader(Module): self.submodules += fifo self.comb += [ - rdata.connect(fifo.sink, omit={"bank", "id", "resp"}), + rdata.connect(fifo.sink, omit={"id", "resp"}), fifo.source.connect(source), data_dequeued.eq(source.valid & source.ready) ] diff --git a/litedram/frontend/ecc.py b/litedram/frontend/ecc.py index f7a4249..5037944 100644 --- a/litedram/frontend/ecc.py +++ b/litedram/frontend/ecc.py @@ -211,7 +211,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR): ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata) self.submodules += ecc_wdata self.comb += [ - port_from.wdata.connect(ecc_wdata.sink, omit={"bank"}), + port_from.wdata.connect(ecc_wdata.sink), ecc_wdata.source.connect(port_to.wdata) ] @@ -223,7 +223,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR): self.submodules += ecc_rdata self.comb += [ ecc_rdata.enable.eq(self.enable.storage), - port_to.rdata.connect(ecc_rdata.sink, omit={"bank"}), + port_to.rdata.connect(ecc_rdata.sink), ecc_rdata.source.connect(port_from.rdata) ]