From 170b3dc67dc785e98e28818104d73844092a877b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 26 Nov 2018 10:37:28 +0100
Subject: [PATCH] frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI

---
 litedram/frontend/wishbone.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index a83bb8b..def0226 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -66,6 +66,7 @@ class LiteDRAMWishbone2AXI(Module):
             )
         )
         fsm.act("WRITE",
+            port.aw.size.eq(ashift),
             port.aw.addr[ashift:].eq(wishbone.adr),
             port.w.last.eq(1),
             port.w.data.eq(wishbone.dat_w),
@@ -84,6 +85,7 @@ class LiteDRAMWishbone2AXI(Module):
             )
         )
         fsm.act("READ",
+            port.ar.size.eq(ashift),
             port.ar.addr[ashift:].eq(wishbone.adr),
             If(port.ar.ready,
                 NextValue(port.ar.valid, 0)