From 180b3d2cc13092923307bc265c3ddc33ee3fb94e Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 27 Dec 2018 22:17:57 +0100
Subject: [PATCH] modules: adjust MT48LC16M16 timings

---
 litedram/modules.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litedram/modules.py b/litedram/modules.py
index d453aa2..3d97c48 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -121,8 +121,8 @@ class MT48LC16M16(SDRAMModule):
     nrows  = 8192
     ncols  = 512
     # timings
-    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=14, tRFC=66, tFAW=None, tRAS=None)}
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=66, tFAW=None, tRAS=44)}
 
 
 class AS4C16M16(SDRAMModule):