From 18d25d84c3667bdb1a72dda80c2665eb58b81412 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ryszard=20R=C3=B3=C5=BCak?= Date: Wed, 30 Mar 2022 12:59:53 +0200 Subject: [PATCH] Update test/reference/*_init.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Ryszard Różak --- test/reference/ddr3_init.h | 3 ++- test/reference/ddr4_init.h | 3 ++- test/reference/sdr_init.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h index 6850c6e..2e6ce47 100644 --- a/test/reference/ddr3_init.h +++ b/test/reference/ddr3_init.h @@ -30,7 +30,8 @@ #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE #define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE #define SDRAM_PHY_READ_LEVELING_CAPABLE -#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8) +#define SDRAM_PHY_DQ_DQS_RATIO 8 +#define SDRAM_PHY_MODULES 8 #define SDRAM_PHY_DELAYS 32 #define SDRAM_PHY_BITSLIPS 8 diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h index 5074a10..7163058 100644 --- a/test/reference/ddr4_init.h +++ b/test/reference/ddr4_init.h @@ -29,7 +29,8 @@ #define SDRAM_PHY_WRITE_LEVELING_CAPABLE #define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE #define SDRAM_PHY_READ_LEVELING_CAPABLE -#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8) +#define SDRAM_PHY_DQ_DQS_RATIO 8 +#define SDRAM_PHY_MODULES 8 #define SDRAM_PHY_DELAYS 512 #define SDRAM_PHY_BITSLIPS 8 diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h index 9054b25..51aff84 100644 --- a/test/reference/sdr_init.h +++ b/test/reference/sdr_init.h @@ -25,7 +25,8 @@ #define SDRAM_PHY_CWL 2 #define SDRAM_PHY_RDPHASE 0 #define SDRAM_PHY_WRPHASE 0 -#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8) +#define SDRAM_PHY_DQ_DQS_RATIO 8 +#define SDRAM_PHY_MODULES 2 void cdelay(int i);