From 18dda2db54e63d95707921b372bbd46d30a66853 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 22 Jun 2019 10:46:02 +0200 Subject: [PATCH] phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits --- litedram/phy/s7ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index 68eb131..3daa2fa 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -62,7 +62,7 @@ class S7DDRPHY(Module, AutoCSR): } half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq])) - self._half_sys8x_taps = CSRStorage(4, reset=half_sys8x_taps) + self._half_sys8x_taps = CSRStorage(5, reset=half_sys8x_taps) if with_odelay: self._wlevel_en = CSRStorage()