diff --git a/litedram/phy/lpddr4/sim.py b/litedram/phy/lpddr4/sim.py
index e556779..54424bf 100644
--- a/litedram/phy/lpddr4/sim.py
+++ b/litedram/phy/lpddr4/sim.py
@@ -9,7 +9,7 @@ from litex.soc.interconnect.stream import ClockDomainCrossing
 from litex.soc.interconnect.csr import AutoCSR
 
 from litedram.common import TappedDelayLine, tXXDController
-from litedram.phy.lpddr4.utils import delayed, once, SimLogger
+from litedram.phy.lpddr4.utils import delayed, edge, SimLogger
 from litedram.phy.lpddr4.commands import MPC
 
 
@@ -75,14 +75,11 @@ class PulseTiming(Module):
         tctrl = tXXDController(t)
         self.submodules += tctrl
 
-        self.sync += [
-            If(self.trigger, triggered.eq(1)),
-            ready_d.eq(tctrl.ready),
-        ]
+        self.sync += If(self.trigger, triggered.eq(1)),
         self.comb += [
             self.ready.eq(triggered & tctrl.ready),
-            self.ready_p.eq(self.ready & ~ready_d),
-            once(self, self.trigger, tctrl.valid.eq(1)),
+            self.ready_p.eq(edge(self, self.ready)),
+            tctrl.valid.eq(edge(self, self.trigger)),
         ]
 
 
@@ -223,7 +220,7 @@ class CommandsSim(Module, AutoCSR):  # clock domain: clk_p
         fsm.act("NORMAL",
             cmds_enabled.eq(1),
             self.tzqlat.trigger.eq(1),
-            once(self, init_delays & self.handle_cmd & ~self.tzqlat.ready,
+            If(init_delays & self.handle_cmd & ~self.tzqlat.ready,
                 self.log.warn("tZQLAT violated")
             ),
         )
diff --git a/litedram/phy/lpddr4/utils.py b/litedram/phy/lpddr4/utils.py
index 227bdf6..a3ed008 100644
--- a/litedram/phy/lpddr4/utils.py
+++ b/litedram/phy/lpddr4/utils.py
@@ -24,10 +24,11 @@ def delayed(mod, sig, cycles=1, **kwargs):
     mod.submodules += delay
     return delay.output
 
-def once(mod, cond, *ops):
-    sig = Signal()
-    mod.sync += If(cond, sig.eq(1))
-    return If(~sig & cond, *ops)
+def edge(mod, cond):
+    """Get a signal that is high on a rising edge of `cond`"""
+    cond_d = Signal()
+    mod.sync += cond_d.eq(cond)
+    return  ~cond_d & cond
 
 class ConstBitSlip(Module):
     def __init__(self, dw, i=None, o=None, slp=None, cycles=1):
@@ -203,9 +204,7 @@ class SimLogger(Module, AutoCSR):
     def log(self, fmt, *args, level=DEBUG, once=True):
         cond = Signal()
         if once:  # make the condition be triggered only on rising edge
-            cond_d = Signal()
-            self.sync += cond_d.eq(cond)
-            condition = ~cond_d & cond
+            condition = edge(self, cond)
         else:
             condition = cond