diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index 7aea3cd..fec6dcd 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -50,7 +50,7 @@ class LiteDRAMCrossbar(Module):
             data_width=self.controller.data_width,
             clock_domain="sys",
             id=len(self.masters),
-            with_bank=self.controller.settigns.with_reordering)
+            with_bank=self.controller.settings.with_reordering)
         self.masters.append(port)
 
         # clock domain crossing
diff --git a/test/test_examples.py b/test/test_examples.py
new file mode 100644
index 0000000..3f31525
--- /dev/null
+++ b/test/test_examples.py
@@ -0,0 +1,21 @@
+import unittest
+import os
+
+
+def build_config(name):
+    errors = 0
+    os.system("rm -rf examples/build")
+    os.system("cd examples && python3 litedram_gen.py {}_config.py".format(name))
+    errors += not os.path.isfile("examples/build/gateware/litedram_core.v")
+    os.system("rm -rf examples/build")
+    return errors
+
+
+class TestExamples(unittest.TestCase):
+    def test_arty(self):
+        errors = build_config("arty")
+        self.assertEqual(errors, 0)
+
+    def test_genesys2(self):
+        errors = build_config("genesys2")
+        self.assertEqual(errors, 0)