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Merge pull request #314 from antmicro/msieron/fix-ddr4-sim 

Fix DFITimingsChecker for DDR4 simulation
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enjoy-digital 2022-11-18 12:47:13 +01:00 committed by GitHub
parent c770dd62ed f25604c153
commit 1f1ab2d3ea
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1 changed files with 4 additions and 6 deletions
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10
litedram/phy/model.py
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@ -199,17 +199,12 @@ class DFITimingsChecker(Module):
return self.ns_to_ps(max(c, t)) return self.ns_to_ps(max(c, t))
def prepare_timings(self, timings, refresh_mode, memtype): def prepare_timings(self, timings, refresh_mode, memtype):
CK_NS = ["tRFC", "tWTR", "tFAW", "tCCD", "tRRD", "tZQCS"]
REF = ["tREFI", "tRFC"]
self.timings = timings self.timings = timings
new_timings = {} new_timings = {}
tck = self.timings["tCK"] tck = self.timings["tCK"]
for key, val in self.timings.items(): for key, val in self.timings.items():
if refresh_mode is not None and key in REF:
val = val[refresh_mode]
if val is None: if val is None:
val = 0 val = 0
elif key == "tCK": elif key == "tCK":
@ -561,9 +556,12 @@ class SDRAMPHYModel(Module):
# DFI timing checker ----------------------------------------------------------------------- # DFI timing checker -----------------------------------------------------------------------
if verbosity > SDRAM_VERBOSE_OFF: if verbosity > SDRAM_VERBOSE_OFF:
timings = {"tCK": (1e9 / clk_freq) / nphases} timings = {"tCK": (1e9 / clk_freq) / nphases}
CK_NS = ["tRFC", "tWTR", "tFAW", "tCCD", "tRRD", "tZQCS"]
REF = ["tREFI", "tRFC"]
for name in _speedgrade_timings + _technology_timings: for name in _speedgrade_timings + _technology_timings:
timings[name] = self.module.get(name) key = self.module.timing_settings.fine_refresh_mode if name in REF else None
timings[name] = self.module.get(name, key)
timing_checker = DFITimingsChecker( timing_checker = DFITimingsChecker(
dfi = self.dfi, dfi = self.dfi,