From 1f7d9eb0b99162c0a671aaebf17d963eb49f6cbc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 14 May 2020 11:44:32 +0200 Subject: [PATCH] litedram_gen: pass FPGA speedgrade to iodelay_pll. --- litedram/gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 95f285d..0ed3464 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -280,7 +280,7 @@ class LiteDRAMS7DDRPHYCRG(Module): sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90) self.comb += platform.request("pll_locked").eq(sys_pll.locked) - self.submodules.iodelay_pll = iodelay_pll = S7PLL() + self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"]) self.comb += iodelay_pll.reset.eq(rst) iodelay_pll.register_clkin(clk, core_config["input_clk_freq"]) iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])