From 224a423082b93fad2aa3bdf01f9282acff6f6a4a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 8 Jan 2019 17:00:51 +0100 Subject: [PATCH] common: allow setting electrical settings with DDR4 --- litedram/common.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index d50e5ab..f74ecec 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -28,12 +28,12 @@ class PhySettings(Settings): self.set_attributes(locals()) self.cwl = cl if cwl is None else cwl - # Optional DDR3 electrical settings: + # Optional DDR3/DDR4 electrical settings: # rtt_nom: Non-Writes on-die termination impedance # rtt_wr: Writes on-die termination impedance # ron: Output driver impedance def add_electrical_settings(self, rtt_nom, rtt_wr, ron): - assert self.memtype == "DDR3" + assert self.memtype in ["DDR3", "DDR4"] self.set_attributes(locals())