From 24203cfc7b8b0ca5d3e8e6ef6dd2a579924b3ce7 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Wed, 23 Oct 2019 10:01:18 -0400 Subject: [PATCH] frontend/axi: add assertion on matching axi, native port data_width --- litedram/frontend/axi.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py index 5da64e5..f4254e7 100644 --- a/litedram/frontend/axi.py +++ b/litedram/frontend/axi.py @@ -32,6 +32,7 @@ class LiteDRAMAXIPort(AXIInterface): class LiteDRAMAXI2NativeW(Module): def __init__(self, axi, port, buffer_depth, base_address): assert axi.address_width >= log2_int(base_address) + assert axi.data_width == port.data_width self.cmd_request = Signal() self.cmd_grant = Signal() @@ -99,6 +100,7 @@ class LiteDRAMAXI2NativeW(Module): class LiteDRAMAXI2NativeR(Module): def __init__(self, axi, port, buffer_depth, base_address): assert axi.address_width >= log2_int(base_address) + assert axi.data_width == port.data_width self.cmd_request = Signal() self.cmd_grant = Signal()