diff --git a/bench/arty.py b/bench/arty.py index d7b78d8..e33a57a 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -22,8 +22,6 @@ from litex.soc.integration.builder import * from litedram.phy import s7ddrphy from litedram.modules import MT41K128M16 -from liteeth.phy.mii import LiteEthPHYMII - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module, AutoCSR): @@ -33,7 +31,7 @@ class _CRG(Module, AutoCSR): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() + self.clock_domains.cd_uart = ClockDomain() # # # @@ -42,10 +40,9 @@ class _CRG(Module, AutoCSR): main_pll.register_clkin(platform.request("clk100"), 100e6) main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) main_pll.create_clkout(self.cd_clk200, 200e6) - main_pll.create_clkout(self.cd_eth, 25e6) + main_pll.create_clkout(self.cd_uart, 100e6) main_pll.expose_drp() self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) - self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk) sys_clk_counter = Signal(32) self.sync += sys_clk_counter.eq(sys_clk_counter + 1) @@ -88,13 +85,8 @@ class BenchSoC(SoCCore): origin = self.mem_map["main_ram"] ) - # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth"), - with_hw_init_reset = False) - self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + # UARTBone --------------------------------------------------------------------------------- + self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser @@ -125,9 +117,9 @@ def main(): s7_bench_test( freq_min = 60e6, freq_max = 150e6, - freq_step = 10e6, + freq_step = 1e6, vco_freq = soc.crg.main_pll.compute_config()["vco"], - bios_filename = "build/kc705/software/bios/bios.bin", + bios_filename = "build/arty/software/bios/bios.bin", bios_timeout = 10, ) diff --git a/bench/common.py b/bench/common.py index 2f59c29..378bcc2 100644 --- a/bench/common.py +++ b/bench/common.py @@ -113,8 +113,12 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t clkout0_clkreg1 = ClkReg1(s7pll.read(0x08)) + tested_vco_divs = [] for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)): vco_div = int(vco_freq/clk_freq) + if vco_div in tested_vco_divs: + continue + tested_vco_divs.append(vco_div) print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6)) clkout0_clkreg1.high_time = vco_div//2 + vco_div%2 clkout0_clkreg1.low_time = vco_div//2 @@ -131,8 +135,9 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t ctrl.reboot() start = time.time() while (time.time() - start) < bios_timeout: - if wb.regs.uart_xover_rxempty.read() == 0: - print("{:c}".format(wb.regs.uart_xover_rxtx.read()), end="") + if wb.regs.uart_xover_rxfull.read(): + for c in wb.read(wb.regs.uart_xover_rxtx.addr, 16, burst="fixed"): + print("{:c}".format(c), end="") # # # diff --git a/bench/genesys2.py b/bench/genesys2.py index 1c421db..41b8d07 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -22,8 +22,6 @@ from litex.soc.integration.builder import * from litedram.phy import s7ddrphy from litedram.modules import MT41J256M16 -from liteeth.phy.s7rgmii import LiteEthPHYRGMII - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module, AutoCSR): @@ -32,6 +30,7 @@ class _CRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_uart = ClockDomain() # # # @@ -40,6 +39,7 @@ class _CRG(Module, AutoCSR): main_pll.register_clkin(platform.request("clk200"), 200e6) main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) main_pll.create_clkout(self.cd_clk200, 200e6) + main_pll.create_clkout(self.cd_uart, 100e6) main_pll.expose_drp() self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) @@ -84,13 +84,8 @@ class BenchSoC(SoCCore): origin = self.mem_map["main_ram"] ) - # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth"), - with_hw_init_reset = False) - self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + # UARTBone --------------------------------------------------------------------------------- + self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser @@ -121,7 +116,7 @@ def main(): s7_bench_test( freq_min = 60e6, freq_max = 180e6, - freq_step = 10e6, + freq_step = 1e6, vco_freq = soc.crg.main_pll.compute_config()["vco"], bios_filename = "build/genesys2/software/bios/bios.bin", bios_timeout = 10, diff --git a/bench/kc705.py b/bench/kc705.py index 3334008..ef904ac 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -22,8 +22,6 @@ from litex.soc.integration.builder import * from litedram.phy import s7ddrphy from litedram.modules import MT8JTF12864 -from liteeth.phy import LiteEthPHY - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module, AutoCSR): @@ -32,6 +30,7 @@ class _CRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_uart = ClockDomain() # # # @@ -40,6 +39,7 @@ class _CRG(Module, AutoCSR): main_pll.register_clkin(platform.request("clk200"), 200e6) main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) main_pll.create_clkout(self.cd_clk200, 200e6) + main_pll.create_clkout(self.cd_uart, 100e6) main_pll.expose_drp() self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) @@ -84,13 +84,8 @@ class BenchSoC(SoCCore): origin = self.mem_map["main_ram"] ) - # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHY( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth"), - clk_freq = self.clk_freq) - self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + # UARTBone --------------------------------------------------------------------------------- + self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser @@ -121,7 +116,7 @@ def main(): s7_bench_test( freq_min = 60e6, freq_max = 180e6, - freq_step = 10e6, + freq_step = 1e6, vco_freq = soc.crg.main_pll.compute_config()["vco"], bios_filename = "build/kc705/software/bios/bios.bin", bios_timeout = 10, diff --git a/bench/kcu105.py b/bench/kcu105.py index f15d500..767f09e 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -22,8 +22,6 @@ from litex.soc.cores.led import LedChaser from litedram.modules import EDY4016A from litedram.phy import usddrphy -from liteeth.phy.ku_1000basex import KU_1000BASEX - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -32,14 +30,16 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_uart = ClockDomain() # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk125"), 125e6) - pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) + pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) + pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) + pll.create_clkout(self.cd_uart, 100e6) pll.expose_drp() self.specials += [ @@ -89,14 +89,8 @@ class BenchSoC(SoCCore): size = 0x40000000, ) - # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, - data_pads = self.platform.request("sfp", 0), - sys_clk_freq = self.clk_freq) - self.add_csr("ethphy") - self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) - self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") - self.add_etherbone(phy=self.ethphy) + # UARTBone --------------------------------------------------------------------------------- + self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(