diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index 80eb46d..e36a8dc 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -54,6 +54,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
     def __init__(self, port, fifo_depth=16, fifo_buffered=False, with_csr=False):
         assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
         self.port   = port
+        self.enable = enable = Signal(reset=1)
         self.sink   = sink   = stream.Endpoint([("address", port.address_width)])
         self.source = source = stream.Endpoint([("data", port.data_width)])
 
@@ -79,8 +80,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
             self.comb += cmd.size.eq(int(log2(port.data_width//8)))
         self.comb += [
             cmd.addr.eq(sink.address),
-            cmd.valid.eq(sink.valid & request_enable),
-            sink.ready.eq(cmd.ready & request_enable),
+            cmd.valid.eq(enable & sink.valid & request_enable),
+            sink.ready.eq(enable & cmd.ready & request_enable),
             request_issued.eq(cmd.valid & cmd.ready)
         ]
 
@@ -104,8 +105,9 @@ class LiteDRAMDMAReader(Module, AutoCSR):
 
         self.comb += [
             rdata.connect(fifo.sink, omit={"id", "resp"}),
-            fifo.source.connect(source),
-            data_dequeued.eq(source.valid & source.ready)
+            fifo.source.connect(source, omit={"ready"}),
+            fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled.
+            data_dequeued.eq(fifo.source.valid & fifo.source.ready)
         ]
 
         if with_csr:
@@ -125,6 +127,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
         base   = Signal(self.port.address_width)
         offset = Signal(self.port.address_width)
         length = Signal(self.port.address_width)
+        self.comb += self.enable.eq(self._enable.storage)
         self.comb += base.eq(self._base.storage[shift:])
         self.comb += length.eq(self._length.storage[shift:])