diff --git a/litedram/frontend/adaptation.py b/litedram/frontend/adaptation.py
index f0a4d85..cd68475 100644
--- a/litedram/frontend/adaptation.py
+++ b/litedram/frontend/adaptation.py
@@ -18,7 +18,7 @@ class LiteDRAMPortCDC(Module):
 
         # # #
 
-        cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 8)
+        cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 4)
         cmd_fifo = ClockDomainsRenamer({"write": cd_from,
                                         "read": cd_to})(cmd_fifo)
         self.submodules += cmd_fifo
@@ -27,7 +27,7 @@ class LiteDRAMPortCDC(Module):
             cmd_fifo.source.connect(port_to.cmd)
         ]
 
-        wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 8)
+        wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 16)
         wdata_fifo = ClockDomainsRenamer({"write": cd_from,
                                           "read": cd_to})(wdata_fifo)
         self.submodules += wdata_fifo
@@ -36,7 +36,7 @@ class LiteDRAMPortCDC(Module):
             wdata_fifo.source.connect(port_to.wdata)
         ]
 
-        rdata_fifo = stream.AsyncFIFO([("data", dw)], 8)
+        rdata_fifo = stream.AsyncFIFO([("data", dw)], 16)
         rdata_fifo = ClockDomainsRenamer({"write": cd_to,
                                           "read": cd_from})(rdata_fifo)
         self.submodules += rdata_fifo