From 2709efa4a728cc2f34aad53d7b2d4e76cff1e334 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 May 2016 17:11:34 +0200
Subject: [PATCH] frontend/crossbar: remove controller_selected (no longer
 needed)

---
 litedram/common.py            |  2 +-
 litedram/frontend/crossbar.py | 25 +++++++++++--------------
 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/litedram/common.py b/litedram/common.py
index 9f717a8..91c90f1 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -71,7 +71,7 @@ class InternalInterface(Record):
         Record.__init__(self, layout)
 
 
-class UserInterface(Record):
+class UserPort(Record):
     def __init__(self, aw, dw, cmd_buffer_depth, read_latency, write_latency):
         self.aw = aw
         self.dw = dw
diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py
index b435269..a133a42 100644
--- a/litedram/frontend/crossbar.py
+++ b/litedram/frontend/crossbar.py
@@ -26,8 +26,11 @@ class LiteDRAMCrossbar(Module):
     def get_port(self):
         if self.finalized:
             raise FinalizeError
-        port = UserInterface(self.rca_bits + self.bank_bits,
-            self.dw, self.cmd_buffer_depth, self.read_latency, self.write_latency)
+        port = UserPort(self.rca_bits + self.bank_bits,
+                        self.dw,
+                        self.cmd_buffer_depth,
+                        self.read_latency,
+                        self.write_latency)
         self.masters.append(port)
         return port
 
@@ -39,7 +42,6 @@ class LiteDRAMCrossbar(Module):
                                                   self.cba_shift)
 
         controller = self.controller
-        controller_selected = [1]*nmasters
         master_readys = [0]*nmasters
         master_wdata_readys = [0]*nmasters
         master_rdata_valids = [0]*nmasters
@@ -60,7 +62,7 @@ class LiteDRAMCrossbar(Module):
                 master_locked.append(locked)
 
             # arbitrate
-            bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
+            bank_selected = [(ba == nb) & ~locked for ba, locked in zip(m_ba, master_locked)]
             bank_requested = [bs & master.valid for bs, master in zip(bank_selected, self.masters)]
             self.comb += [
                 rr.request.eq(Cat(*bank_requested)),
@@ -99,20 +101,15 @@ class LiteDRAMCrossbar(Module):
         self.comb += [master.rdata_valid.eq(master_rdata_valid) for master, master_rdata_valid in zip(self.masters, master_rdata_valids)]
 
         # route data writes
-        controller_selected_wl = controller_selected
-        for i in range(self.write_latency):
-            n_controller_selected_wl = [Signal() for i in range(nmasters)]
-            self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
-            controller_selected_wl = n_controller_selected_wl
         wdata_maskselect = []
         wdata_we_maskselect = []
-        for master, selected in zip(self.masters, controller_selected_wl):
+        for master in self.masters:
             o_wdata = Signal(self.dw)
             o_wdata_we = Signal(self.dw//8)
-            self.comb += If(selected,
-                    o_wdata.eq(master.wdata),
-                    o_wdata_we.eq(master.wdata_we)
-                )
+            self.comb += [
+                o_wdata.eq(master.wdata),
+                o_wdata_we.eq(master.wdata_we)
+            ]
             wdata_maskselect.append(o_wdata)
             wdata_we_maskselect.append(o_wdata_we)
         self.comb += [