diff --git a/litedram/phy/sim_utils.py b/litedram/phy/sim_utils.py
index 9cd85fc..3a45de8 100644
--- a/litedram/phy/sim_utils.py
+++ b/litedram/phy/sim_utils.py
@@ -4,6 +4,8 @@
 # Copyright (c) 2021 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import re
+
 from migen import *
 
 from litex.build.sim import SimPlatform
@@ -128,6 +130,11 @@ class Platform(SimPlatform):
 
 # Logging ------------------------------------------------------------------------------------------
 
+# Named regex group
+def ng(name, regex):
+    return r"(?P<{}>{})".format(name, regex)
+
+
 class SimLogger(Module, AutoCSR):
     """Logger for use in simulation
 
@@ -151,6 +158,13 @@ class SimLogger(Module, AutoCSR):
     ERROR = 3
     NONE  = 4
 
+    # Regex pattern for parsing logs
+    LOG_PATTERN = re.compile(r"\[\s*{time} ps] \[{level}]\s*{msg}".format(
+        time  = ng("time", r"[0-9]+"),
+        level = ng("level", r"DEBUG|INFO|WARN|ERROR"),
+        msg   = ng("msg", ".*"),
+    ))
+
     def __init__(self, log_level=INFO, clk_freq=None, clk_freq_cd=None, with_csrs=False):
         self.ops = []
         self.level = Signal(reset=log_level, max=self.NONE + 1)
diff --git a/test/test_lpddr4.py b/test/test_lpddr4.py
index 806f8c9..fa869a6 100644
--- a/test/test_lpddr4.py
+++ b/test/test_lpddr4.py
@@ -15,6 +15,7 @@ from migen import *
 
 from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY
 from litedram.phy.lpddr4 import simsoc
+from litedram.phy.sim_utils import SimLogger
 
 import test.phy_common
 from test.phy_common import DFISequencer, PadChecker
@@ -651,18 +652,7 @@ class LPDDR4Tests(unittest.TestCase):
         )
 
 
-# Named regex group
-def ng(name, regex):
-    return r"(?P<{}>{})".format(name, regex)
-
-
 class VerilatorLPDDR4Tests(unittest.TestCase):
-    LOG_PATTERN = re.compile(r"\[\s*{time} ps] \[{level}]\s*{msg}".format(
-        time  = ng("time", r"[0-9]+"),
-        level = ng("level", r"DEBUG|INFO|WARN|ERROR"),
-        msg   = ng("msg", ".*"),
-    ))
-
     # We ignore these 2 warnings, they appear due to the fact that litedram starts
     # in hardware control mode which holds reset_n=1 all the time. PHY will later
     # set reset_n=0 once again and then perform proper init sequence.
@@ -672,7 +662,7 @@ class VerilatorLPDDR4Tests(unittest.TestCase):
     ]
 
     def check_logs(self, logs):
-        for match in self.LOG_PATTERN.finditer(logs):
+        for match in SimLogger.LOG_PATTERN.finditer(logs):
             if match.group("level") in ["WARN", "ERROR"]:
                 allowed = any(
                     lvl == match.group("level") and msg in match.group("msg")