From 2b8af870c581f0d5da5ab2c67bb7188ff06f8f40 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 May 2022 17:34:52 +0200 Subject: [PATCH] phy/usddrphy/Clk: Connect cdly_value only on first clk pad. --- litedram/phy/usddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 708b270..68f0f2a 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -167,7 +167,7 @@ class USDDRPHY(Module, AutoCSR): i_EN_VTC = self._en_vtc.storage, i_CE = self._cdly_inc.re, i_INC = 1, - o_CNTVALUEOUT = self._cdly_value.status, + o_CNTVALUEOUT = self._cdly_value.status if i == 0 else Signal(), i_ODATAIN = clk_o_nodelay, o_DATAOUT = clk_o_delayed, ),