diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index 4be19fc..5d68737 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -43,14 +43,25 @@ class BankMachine(Module):
 
         # Command buffer
         cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))]
-        cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
-        cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
-        self.submodules += cmd_buffer_lookahead, cmd_buffer
+        if settings.with_auto_precharge:
+            cmd_buffer_lookahead = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
+            cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change
+            self.submodules += cmd_buffer_lookahead, cmd_buffer
+            self.comb += [
+                req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
+                                                             "rdata_valid", "rdata_ready",
+                                                             "lock"]),
+                cmd_buffer_lookahead.source.connect(cmd_buffer.sink)
+            ]
+        else:
+            cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth)
+            self.submodules += cmd_buffer
+            self.comb += [
+                req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready",
+                                                   "rdata_valid", "rdata_ready",
+                                                   "lock"])
+            ]
         self.comb += [
-            req.connect(cmd_buffer_lookahead.sink, omit=["wdata_valid", "wdata_ready",
-                                                         "rdata_valid", "rdata_ready",
-                                                         "lock"]),
-            cmd_buffer_lookahead.source.connect(cmd_buffer.sink),
             cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid),
             req.lock.eq(cmd_buffer.source.valid),
         ]
@@ -91,13 +102,14 @@ class BankMachine(Module):
                                                     cmd.is_write))
 
         # Auto Precharge
-        self.comb += [
-            If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
-                If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
-                    auto_precharge.eq(self.precharge_timer.done & (track_close == 0))
+        if settings.with_auto_precharge:
+            self.comb += [
+                If(cmd_buffer_lookahead.source.valid & cmd_buffer.source.valid,
+                    If(slicer.row(cmd_buffer_lookahead.source.adr) != slicer.row(cmd_buffer.source.adr),
+                        auto_precharge.eq(self.precharge_timer.done & (track_close == 0))
+                    )
                 )
-            )
-        ]
+            ]
 
         # Control and command generation FSM
         # Note: tRRD, tFAW, tCCD, tWTR timings are enforced by the multiplexer
diff --git a/litedram/core/controller.py b/litedram/core/controller.py
index 870802b..01065aa 100644
--- a/litedram/core/controller.py
+++ b/litedram/core/controller.py
@@ -10,12 +10,14 @@ from litedram.core.multiplexer import *
 class ControllerSettings:
     def __init__(self, cmd_buffer_depth=8, read_time=32, write_time=16,
                  with_bandwidth=False,
-                 with_refresh=True):
+                 with_refresh=True,
+                 with_auto_precharge=False):
         self.cmd_buffer_depth = cmd_buffer_depth
         self.read_time = read_time
         self.write_time = write_time
         self.with_bandwidth = with_bandwidth
         self.with_refresh = with_refresh
+        self.with_auto_precharge = with_auto_precharge
 
 
 class LiteDRAMController(Module):