From 2e3e19e9d449120d32d2f9f0b6d8a227c1b9229f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 27 Aug 2020 18:41:54 +0200 Subject: [PATCH] bench: simplify/improve, working on arty/genesys2. --- bench/arty.py | 45 +++++++++++++++++++++------------------------ bench/genesys2.py | 41 +++++++++++++++++++---------------------- bench/kcu105.py | 28 ++++++++++++---------------- 3 files changed, 52 insertions(+), 62 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 9a1a1a4..a312a84 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -40,7 +40,7 @@ class _CRG(Module, AutoCSR): self.submodules.main_pll = main_pll = S7PLL(speedgrade=-1) self.comb += main_pll.reset.eq(~platform.request("cpu_reset")) main_pll.register_clkin(platform.request("clk100"), 100e6) - main_pll.create_clkout(self.cd_sys_pll, 100e6) + main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) main_pll.create_clkout(self.cd_clk200, 200e6) main_pll.create_clkout(self.cd_eth, 25e6) main_pll.expose_drp() @@ -54,7 +54,7 @@ class _CRG(Module, AutoCSR): self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~main_pll.locked) - pll.register_clkin(self.cd_sys_pll.clk, 100e6) + pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) @@ -62,7 +62,7 @@ class _CRG(Module, AutoCSR): # Bench SoC ---------------------------------------------------------------------------------------- class BenchSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6)): + def __init__(self, sys_clk_freq=int(150e6)): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -98,12 +98,14 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser - self.submodules.led = LedChaser(self.platform.request_all("user_led"), sys_clk_freq) - self.add_csr("led") + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") # Bench Test --------------------------------------------------------------------------------------- -def bench_test(): +def bench_test(vco_freq): import time from litex import RemoteClient @@ -122,7 +124,7 @@ def bench_test(): from litex.soc.integration.common import get_mem_data rom_data = get_mem_data(filename, "little") for i, data in enumerate(rom_data): - wb.write(wb.mems.rom.base + 4*i) + wb.write(wb.mems.rom.base + 4*i, data) class ClkReg1: def __init__(self, value=0): @@ -204,21 +206,17 @@ def bench_test(): ctrl = SoCCtrl() ctrl.load_rom("build/arty/software/bios/bios.bin") - ctrl.reset() - - vco_freq = 1.6e9 + ctrl.reboot() s7pll = S7PLL() - print("Dump Main PLL...") clkout0_clkreg1 = ClkReg1(s7pll.read(0x08)) - print(clkout0_clkreg1) - for i in range(12, 44, 2): - sys_clk_freq = vco_freq/i - print("Reconfig Main PLL to {}MHz...".format(sys_clk_freq/1e6)) - clkout0_clkreg1.high_time = i//2 + i%2 - clkout0_clkreg1.low_time = i//2 + for clk_freq in range(int(60e6), int(150e6), int(10e6)): + vco_div = int(vco_freq/clk_freq) + print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6)) + clkout0_clkreg1.high_time = vco_div//2 + vco_div%2 + clkout0_clkreg1.low_time = vco_div//2 s7pll.write(0x08, clkout0_clkreg1.pack()) print("Measuring sys_clk...") @@ -228,8 +226,8 @@ def bench_test(): end = wb.regs.crg_sys_clk_counter.read() print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration))) - print("Reset SoC and get BIOS log...") - ctrl.reset() + print("Reboot SoC and get BIOS log...") + ctrl.reboot() start = time.time() while (time.time() - start) < 5: if wb.regs.uart_xover_rxempty.read() == 0: @@ -248,17 +246,16 @@ def main(): parser.add_argument("--test", action="store_true", help="Run Test") args = parser.parse_args() - if args.build or args.load: - soc = BenchSoC() - builder = Builder(soc, csr_csv="csr.csv") - builder.build(run=args.build) + soc = BenchSoC() + builder = Builder(soc, csr_csv="csr.csv") + builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if args.test: - bench_test() + bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"]) if __name__ == "__main__": main() diff --git a/bench/genesys2.py b/bench/genesys2.py index 5cc0e4f..dad83ac 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -38,24 +38,26 @@ class _CRG(Module, AutoCSR): self.submodules.main_pll = main_pll = S7PLL(speedgrade=-2) self.comb += main_pll.reset.eq(~platform.request("cpu_reset_n")) main_pll.register_clkin(platform.request("clk200"), 200e6) - main_pll.create_clkout(self.cd_sys_pll, 200e6) + main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) main_pll.create_clkout(self.cd_clk200, 200e6) main_pll.expose_drp() self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + sys_clk_counter = Signal(32) self.sync += sys_clk_counter.eq(sys_clk_counter + 1) self.sys_clk_counter = CSRStatus(32) self.comb += self.sys_clk_counter.status.eq(sys_clk_counter) + self.submodules.pll = pll = S7PLL(speedgrade=-2) self.comb += pll.reset.eq(~main_pll.locked) - pll.register_clkin(self.cd_sys_pll.clk, 200e6) + pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) # Bench SoC ---------------------------------------------------------------------------------------- class BenchSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6)): + def __init__(self, sys_clk_freq=int(175e6)): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -97,7 +99,7 @@ class BenchSoC(SoCCore): # Bench Test --------------------------------------------------------------------------------------- -def bench_test(): +def bench_test(vco_freq): import time from litex import RemoteClient @@ -116,7 +118,7 @@ def bench_test(): from litex.soc.integration.common import get_mem_data rom_data = get_mem_data(filename, "little") for i, data in enumerate(rom_data): - wb.write(wb.mems.rom.base + 4*i) + wb.write(wb.mems.rom.base + 4*i, data) class ClkReg1: def __init__(self, value=0): @@ -198,21 +200,17 @@ def bench_test(): ctrl = SoCCtrl() ctrl.load_rom("build/genesys2/software/bios/bios.bin") - ctrl.reset() - - vco_freq = 1.8e9 + ctrl.reboot() s7pll = S7PLL() - print("Dump Main PLL...") clkout0_clkreg1 = ClkReg1(s7pll.read(0x08)) - print(clkout0_clkreg1) - for i in range(7, 14): - sys_clk_freq = (125e6/200e6)*(vco_freq/i) - print("Reconfig Main PLL to {}MHz...".format(sys_clk_freq/1e6)) - clkout0_clkreg1.high_time = i//2 + i%2 - clkout0_clkreg1.low_time = i//2 + for clk_freq in range(int(60e6), int(180e6), int(10e6)): + vco_div = int(vco_freq/clk_freq) + print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6)) + clkout0_clkreg1.high_time = vco_div//2 + vco_div%2 + clkout0_clkreg1.low_time = vco_div//2 s7pll.write(0x08, clkout0_clkreg1.pack()) print("Measuring sys_clk...") @@ -222,8 +220,8 @@ def bench_test(): end = wb.regs.crg_sys_clk_counter.read() print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration))) - print("Reset SoC and get BIOS log...") - ctrl.reset() + print("Reboot SoC and get BIOS log...") + ctrl.reboot() start = time.time() while (time.time() - start) < 5: if wb.regs.uart_xover_rxempty.read() == 0: @@ -242,17 +240,16 @@ def main(): parser.add_argument("--test", action="store_true", help="Run Test") args = parser.parse_args() - if args.build or args.load: - soc = BenchSoC() - builder = Builder(soc, csr_csv="csr.csv") - builder.build(run=args.build) + soc = BenchSoC() + builder = Builder(soc, csr_csv="csr.csv") + builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if args.test: - bench_test() + bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"]) if __name__ == "__main__": main() diff --git a/bench/kcu105.py b/bench/kcu105.py index 75329dc..0a81adb 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -73,6 +73,7 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + self.add_csr("crg") # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), @@ -88,7 +89,7 @@ class BenchSoC(SoCCore): size = 0x40000000, ) - # Ethebone --------------------------------------------------------------------------------- + # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, data_pads = self.platform.request("sfp", 0), sys_clk_freq = self.clk_freq) @@ -105,7 +106,7 @@ class BenchSoC(SoCCore): # Bench Test --------------------------------------------------------------------------------------- -def bench_test(): +def bench_test(sys_clk_freq, vco_freq): import time from litex import RemoteClient @@ -124,7 +125,7 @@ def bench_test(): from litex.soc.integration.common import get_mem_data rom_data = get_mem_data(filename, "little") for i, data in enumerate(rom_data): - wb.write(wb.mems.rom.base + 4*i) + wb.write(wb.mems.rom.base + 4*i, data) class ClkReg1: def __init__(self, value=0): @@ -206,20 +207,16 @@ def bench_test(): ctrl = SoCCtrl() ctrl.load_rom("build/kcu105/software/bios/bios.bin") - ctrl.reset() - - vco_freq = 1e9 + ctrl.reboot() uspll = USPLL() - print("Dump Main PLL...") - clkout0_clkreg1 = ClkReg1(uspll.read(0x08)) - print(clkout0_clkreg1) + clkout0_clkreg1 = ClkReg1(s7pll.read(0x08)) # TODO: add dynamic freq test. - print("Reset SoC and get BIOS log...") - ctrl.reset() + print("Reboot SoC and get BIOS log...") + ctrl.reboot() start = time.time() while (time.time() - start) < 5: if wb.regs.uart_xover_rxempty.read() == 0: @@ -238,17 +235,16 @@ def main(): parser.add_argument("--test", action="store_true", help="Run Test") args = parser.parse_args() - if args.build or args.load: - soc = BenchSoC() - builder = Builder(soc, csr_csv="csr.csv") - builder.build(run=args.build) + soc = BenchSoC() + builder = Builder(soc, csr_csv="csr.csv") + builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if args.test: - bench_test() + bench_test(vco_freq=soc.crg.main_pll.compute_config()["vco"]) if __name__ == "__main__": main()