From 33f3aa55e57c2e4713d664a20016582a22288df0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 16 Dec 2020 11:49:33 +0100 Subject: [PATCH] phy/ecp5ddrphy: add DM remapping capability. Required on OrangeCrab that has LDM/UDM swapped. --- litedram/phy/ecp5ddrphy.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/phy/ecp5ddrphy.py b/litedram/phy/ecp5ddrphy.py index f6b9190..912cbcc 100644 --- a/litedram/phy/ecp5ddrphy.py +++ b/litedram/phy/ecp5ddrphy.py @@ -112,7 +112,7 @@ class ECP5DDRPHYInit(Module): # Lattice ECP5 DDR PHY ----------------------------------------------------------------------------- class ECP5DDRPHY(Module, AutoCSR): - def __init__(self, pads, sys_clk_freq=100e6): + def __init__(self, pads, sys_clk_freq=100e6, dm_remapping={}): pads = PHYPadsCombiner(pads) memtype = "DDR3" tck = 2/(2*2*sys_clk_freq) @@ -300,7 +300,7 @@ class ECP5DDRPHY(Module, AutoCSR): dm_o_data_d = Signal(8) dm_o_data_muxed = Signal(4) for n in range(8): - self.comb += dm_o_data[n].eq(dfi.phases[n//4].wrdata_mask[n%4*databits//8+i]) + self.comb += dm_o_data[n].eq(dfi.phases[n//4].wrdata_mask[n%4*databits//8+dm_remapping.get(i, i)]) self.sync += dm_o_data_d.eq(dm_o_data) dm_bl8_cases = {} dm_bl8_cases[0] = dm_o_data_muxed.eq(dm_o_data[:4])