From 33ff34b622af9f9231d1b61a5a3d77caae16617f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Dec 2018 17:46:43 +0100 Subject: [PATCH] core/refresher: use self.sync to fix build (verilog wire vs reg...) --- litedram/core/refresher.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/core/refresher.py b/litedram/core/refresher.py index ee995a4..7fff55c 100644 --- a/litedram/core/refresher.py +++ b/litedram/core/refresher.py @@ -35,7 +35,7 @@ class RefreshGenerator(Module): ]) ]) ] - self.comb += [ + self.sync += [ cmd.a.eq(2**10), cmd.ba.eq(0), cmd.cas.eq(0),