From 361d250677dc2a96865c21ea8db72fd0cb4cd1ee Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 3 Jun 2020 09:04:00 +0200 Subject: [PATCH] litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide). --- litedram/gen.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/litedram/gen.py b/litedram/gen.py index 149b3c3..5117492 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -277,6 +277,7 @@ class LiteDRAMS7DDRPHYCRG(Module): self.submodules.sys_pll = sys_pll = S7PLL(speedgrade=core_config["speedgrade"]) self.comb += sys_pll.reset.eq(rst) sys_pll.register_clkin(clk, core_config["input_clk_freq"]) + sys_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) sys_pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"]) if core_config["memtype"] == "DDR2": sys_pll.create_clkout(self.cd_sys2x, 2*core_config["sys_clk_freq"]) @@ -289,10 +290,6 @@ class LiteDRAMS7DDRPHYCRG(Module): self.comb += platform.request("pll_locked").eq(sys_pll.locked) - self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"]) - self.comb += iodelay_pll.reset.eq(rst) - iodelay_pll.register_clkin(clk, core_config["input_clk_freq"]) - iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay) # LiteDRAMCoreControl ------------------------------------------------------------------------------