From 36d5b42aa03edb10a3580426bce69be983a39b76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 17 Mar 2020 15:37:50 +0100 Subject: [PATCH] test: correct DMAReaderDriver/DMAWriterDriver logic --- test/test_bist.py | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/test/test_bist.py b/test/test_bist.py index 890e863..29980e0 100644 --- a/test/test_bist.py +++ b/test/test_bist.py @@ -95,8 +95,7 @@ class DMAWriterDriver: yield self.dma.sink.data.eq(data) while not (yield self.dma.sink.ready): yield - while (yield self.dma.sink.ready): - yield + yield yield self.dma.sink.valid.eq(0) @staticmethod @@ -104,8 +103,7 @@ class DMAWriterDriver: for _ in range(n): while not (yield port.wdata.ready): yield - while (yield port.wdata.ready): - yield + yield class DMAReaderDriver: @@ -130,10 +128,8 @@ class DMAReaderDriver: def read_handler(self): yield self.dma.source.ready.eq(1) while True: - while not (yield self.dma.source.valid): - yield - data = (yield self.dma.source.data) - self.data.append(data) + if (yield self.dma.source.valid): + self.data.append((yield self.dma.source.data)) yield