From 370b05ecf1b77976190855e75c444317d2e69923 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Jul 2018 17:27:47 +0200 Subject: [PATCH] core/bankmachine: add Four Activate Window support (tFAW) --- litedram/common.py | 3 +- litedram/core/bankmachine.py | 22 ++++++-- litedram/modules.py | 100 +++++++++++++++++++++++------------ 3 files changed, 88 insertions(+), 37 deletions(-) diff --git a/litedram/common.py b/litedram/common.py index 539cb41..65fda07 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -31,13 +31,14 @@ class GeomSettings: class TimingSettings: - def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC): + def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW): self.tRP = tRP self.tRCD = tRCD self.tWR = tWR self.tWTR = tWTR self.tREFI = tREFI self.tRFC = tRFC + self.tFAW = tFAW def cmd_layout(aw): diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index c9068b6..253a44d 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -37,8 +37,6 @@ class BankMachine(Module): # # # - auto_precharge = Signal() - slicer = _AddressSlicer(settings.geom.colbits, address_align) # Command buffer @@ -71,6 +69,7 @@ class BankMachine(Module): ) # Auto Precharge + auto_precharge = Signal() self.comb += [ # If both buffers have data to output, check row to see # if we can embed an autoprecharge in current cmd. @@ -81,6 +80,20 @@ class BankMachine(Module): ) ] + # Four Activate Window + activate = Signal() + activate_allowed = Signal(reset=1) + tfaw = settings.timing.tFAW + if tfaw is not None: + activate_count = Signal(max=tfaw) + activate_window = Signal(tfaw) + self.sync += activate_window.eq(Cat(activate, activate_window)) + for i in range(tfaw): + next_activate_count = Signal(max=tfaw) + self.comb += next_activate_count.eq(activate_count + activate_window[i]) + activate_count = next_activate_count + self.comb += If(activate_count >=4, activate_allowed.eq(0)) + # Address generation sel_row_adr = Signal() self.comb += [ @@ -126,7 +139,9 @@ class BankMachine(Module): NextState("PRECHARGE") ) ).Else( - NextState("ACTIVATE") + If(activate_allowed, + NextState("ACTIVATE") + ) ) ) ) @@ -151,6 +166,7 @@ class BankMachine(Module): track_close.eq(1) ) fsm.act("ACTIVATE", + activate.eq(1), sel_row_adr.eq(1), track_open.eq(1), cmd.valid.eq(1), diff --git a/litedram/modules.py b/litedram/modules.py index 769195e..0533b74 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -4,6 +4,9 @@ from migen import * from litedram.common import GeomSettings, TimingSettings +# TODO: +# - add speedgrade support +# - specify tWTR, tFAW in ck or ns class SDRAMModule: def __init__(self, clk_freq, rate): @@ -18,9 +21,10 @@ class SDRAMModule: tRP=self.ns(self.tRP), tRCD=self.ns(self.tRCD), tWR=self.ns(self.tWR), - tWTR=self.tWTR, tREFI=self.ns(self.tREFI, False), - tRFC=self.ns(self.tRFC) + tRFC=self.ns(self.tRFC), + tWTR=self.tWTR, + tFAW=None if not hasattr(self, "tFAW") else self.tFAW ) def ns(self, t, margin=True): @@ -42,13 +46,15 @@ class IS42S16160(SDRAMModule): nbanks = 4 nrows = 8192 ncols = 512 - # timings (-7 speedgrade) + # timings (ns) tRP = 20 tRCD = 20 tWR = 20 - tWTR = 2 tREFI = 64*1000*1000/8192 tRFC = 70 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None class MT48LC4M16(SDRAMModule): @@ -57,13 +63,15 @@ class MT48LC4M16(SDRAMModule): nbanks = 4 nrows = 4096 ncols = 256 - # timings (-7 speedgrade) + # timings (ns) tRP = 15 tRCD = 15 tWR = 14 - tWTR = 2 tREFI = 64*1000*1000/4096 tRFC = 66 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None class AS4C16M16(SDRAMModule): @@ -72,13 +80,16 @@ class AS4C16M16(SDRAMModule): nbanks = 4 nrows = 8192 ncols = 512 - # timings (-6 speedgrade) + # timings (ns) tRP = 18 tRCD = 18 tWR = 12 - tWTR = 2 + tREFI = 64*1000*1000/8192 tRFC = 60 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None # DDR @@ -88,13 +99,15 @@ class MT46V32M16(SDRAMModule): nbanks = 4 nrows = 8192 ncols = 1024 - # timings (-6 speedgrade) + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 64*1000*1000/8192 tRFC = 70 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None # LPDDR @@ -104,13 +117,15 @@ class MT46H32M16(SDRAMModule): nbanks = 4 nrows = 8192 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 64*1000*1000/8192 tRFC = 72 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None class MT46H32M32(SDRAMModule): memtype = "LPDDR" @@ -118,13 +133,15 @@ class MT46H32M32(SDRAMModule): nbanks = 4 nrows = 8192 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 64*1000*1000/8192 tRFC = 72 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None # DDR2 @@ -134,13 +151,15 @@ class MT47H128M8(SDRAMModule): nbanks = 8 nrows = 16384 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 7800 tRFC = 127.5 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None class MT47H64M16(SDRAMModule): @@ -149,13 +168,15 @@ class MT47H64M16(SDRAMModule): nbanks = 8 nrows = 8192 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 7800 tRFC = 127.5 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = None class P3R1GE4JGF(SDRAMModule): @@ -164,14 +185,15 @@ class P3R1GE4JGF(SDRAMModule): nbanks = 8 nrows = 8192 ncols = 1024 - # timings + # timings (ns) tRP = 12.5 tRCD = 12.5 tWR = 15 - tWTR = 3 tREFI = 7800 tRFC = 127.5 - + # timings (sys_clk cycles) + tWTR = 3 + tFAW = None # DDR3 class MT8JTF12864(SDRAMModule): @@ -180,13 +202,15 @@ class MT8JTF12864(SDRAMModule): nbanks = 8 nrows = 16384 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 2 tREFI = 7800 tRFC = 70 + # timings (sys_clk cycles) + tWTR = 2 + tFAW = ceil(32/4) class MT41J128M16(SDRAMModule): @@ -195,13 +219,15 @@ class MT41J128M16(SDRAMModule): nbanks = 8 nrows = 16384 ncols = 1024 - # timings + # timings (ns) tRP = 15 tRCD = 15 tWR = 15 - tWTR = 3 tREFI = 64*1000*1000/16384 tRFC = 260 + # timings (sys_clk cycles) + tWTR = 3 + tFAW = ceil(32/4) class MT41K128M16(SDRAMModule): @@ -210,13 +236,15 @@ class MT41K128M16(SDRAMModule): nbanks = 8 nrows = 16384 ncols = 1024 - # timings (-7 speedgrade) + # timings (ns) tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 160 + # timings (sys_clk cycles) + tWTR = 3 + tFAW = ceil(32/4) class MT41K256M16(SDRAMModule): @@ -225,13 +253,15 @@ class MT41K256M16(SDRAMModule): nbanks = 8 nrows = 32768 ncols = 1024 - # timings (-7 speedgrade) + # timings (ns) tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260 + # timings (sys_clk cycles) + tWTR = 3 + tFAW = ceil(32/4) class MT41J256M16(SDRAMModule): @@ -240,13 +270,15 @@ class MT41J256M16(SDRAMModule): nbanks = 8 nrows = 32768 ncols = 1024 - # timings (-125 speedgrade) + # timings (ns) tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260 + # timings (sys_clk cycles) + tWTR = 3 + tFAW = ceil(32/4) class MT18KSF1G72HZ_1G6(SDRAMModule): @@ -255,10 +287,12 @@ class MT18KSF1G72HZ_1G6(SDRAMModule): nbanks = 8 nrows = 65536 ncols = 1024 - # timings (-125 speedgrade) + # timings (ns) tRP = 13.75 tRCD = 13.75 tWR = 15 - tWTR = 3 tREFI = 64*1000*1000/8192 tRFC = 260 + # timings (sys_clk cycles) + tWTR = 3 + tFAW = ceil(32/4)