bench: Update with LiteX/LiteX-Boards changes.

bench/common.py

@@ -101,7 +101,7 @@ class BenchController:
 
     def load_rom(self, filename, delay=0):
         from litex.soc.integration.common import get_mem_data
-        rom_data = get_mem_data(filename, "little")
+        rom_data = get_mem_data(filename, endianness="little")
         for i, data in enumerate(rom_data):
             self.bus.write(self.bus.mems.rom.base + 4*i, data)
             print(f"{(i+1)*4}/{len(rom_data*4)} bytes\r", end="")

bench/xcu1525.py

@@ -12,7 +12,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import xilinx_xcu1525
+from litex_boards.platforms import sqrl_xcu1525
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *
@@ -74,7 +74,7 @@ class _CRG(Module, AutoCSR):
 
 class BenchSoC(SoCCore):
     def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False, with_analyzer=False):
-        platform = xilinx_xcu1525.Platform()
+        platform = sqrl_xcu1525.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
@@ -136,7 +136,7 @@ def main():
     args = parser.parse_args()
 
     soc     = BenchSoC(uart=args.uart, channel=int(args.channel, 0), with_bist=args.with_bist, with_analyzer=args.with_analyzer)
-    builder = Builder(soc, output_dir=f"build/xilinx_xcu1525_ch{args.channel}", csr_csv="csr.csv")
+    builder = Builder(soc, output_dir=f"build/sqrl_xcu1525_ch{args.channel}", csr_csv="csr.csv")
     builder.build(run=args.build)
 
     if args.load:
@@ -145,7 +145,7 @@ def main():
 
     if args.load_bios:
         from common import load_bios
-        load_bios(f"build/xilinx_xcu1525_ch{args.channel}/software/bios/bios.bin")
+        load_bios(f"build/sqrl_xcu1525_ch{args.channel}/software/bios/bios.bin")
 
     if args.sys_clk_freq is not None:
         from common import us_set_sys_clk
@@ -158,7 +158,7 @@ def main():
             freq_max      = 180e6,
             freq_step     = 1e6,
             vco_freq      = soc.crg.pll.compute_config()["vco"],
-            bios_filename = f"build/xilinx_xcu1525_ch{args.channel}/software/bios/bios.bin")
+            bios_filename = f"build/sqrl_xcu1525_ch{args.channel}/software/bios/bios.bin")
 
 if __name__ == "__main__":
     main()

litedram/phy/rpc/arty.py

@@ -346,7 +346,7 @@ def reboot(wb):
 
 def load_rom(wb, filename):
     from litex.soc.integration.common import get_mem_data
-    rom_data = get_mem_data(filename, "little")
+    rom_data = get_mem_data(filename, endianness="little")
     print(f"load bios from: {filename} starting at 0x{wb.mems.rom.base:08x}")
     for i, data in enumerate(rom_data):
         wb.write(wb.mems.rom.base + 4*i, data)

litedram/phy/rpc/simsoc.py

@@ -315,7 +315,7 @@ def main():
         soc_kwargs["uart_name"] = "sim"
         sim_config.add_module("serial2console", "serial")
     if args.rom_init:
-        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu.endianness)
+        soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, endianness=cpu.endianness)
     args.with_sdram = True
     soc_kwargs["integrated_main_ram_size"] = 0x0
     soc_kwargs["sdram_verbosity"]          = int(args.sdram_verbosity)
@@ -326,7 +326,7 @@ def main():
         trace_reset    = args.trace_reset,
         auto_precharge = args.auto_precharge,
         with_refresh   = not args.no_refresh,
-        sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
+        sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, endianness=cpu.endianness),
         l2_size        = args.l2_size,
         **soc_kwargs)