diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py
index a60c5fa..1f0d4ba 100644
--- a/litedram/frontend/bist.py
+++ b/litedram/frontend/bist.py
@@ -42,7 +42,7 @@ class Counter(Module):
 
 class _LiteDRAMBISTGenerator(Module):
     def __init__(self, dram_port, random):
-        self.shoot = Signal()
+        self.start = Signal()
         self.done = Signal()
         self.base = Signal(dram_port.aw)
         self.length = Signal(dram_port.aw)
@@ -50,39 +50,41 @@ class _LiteDRAMBISTGenerator(Module):
         # # #
 
         self.submodules.dma = dma = LiteDRAMDMAWriter(dram_port)
+        gen_cls = LFSR if random else Counter
+        self.submodules.gen = gen = gen_cls(dram_port.dw)
 
-        if random:
-        	self.submodules.gen = gen = LFSR(dram_port.dw)
-        else:
-        	self.submodules.gen = gen = Counter(dram_port.dw)
+        offset = Signal(dram_port.aw)
 
-        shooted = Signal()
-        enable = Signal()
-        counter = Signal(dram_port.aw)
-        self.comb += enable.eq(shooted & (counter != (self.length - 1)))
-        self.sync += [
-            If(self.shoot,
-                shooted.eq(1),
-                counter.eq(0)
-            ).Elif(gen.ce,
-                counter.eq(counter + 1)
+        fsm = FSM(reset_state="IDLE")
+        self.submodules += fsm
+
+        fsm.act("IDLE",
+            self.done.eq(1),
+            If(self.start,
+                NextValue(offset, 0),
+                NextState("RUN")
             )
-        ]
-
+        )
+        fsm.act("RUN",
+            dma.sink.valid.eq(1),
+            If(dma.sink.ready,
+                gen.ce.eq(1),
+                NextValue(offset, offset + 1),
+                If(offset == (self.length-1),
+                    NextState("IDLE")
+                )
+            )
+        )
         self.comb += [
-            dma.sink.valid.eq(enable),
-            dma.sink.address.eq(self.base + counter),
-            dma.sink.data.eq(gen.o),
-            gen.ce.eq(enable & dma.sink.ready),
-
-            self.done.eq(~enable)
+            dma.sink.address.eq(self.base + offset),
+            dma.sink.data.eq(gen.o)
         ]
 
 
 class LiteDRAMBISTGenerator(Module, AutoCSR):
     def __init__(self, dram_port, random=True):
-        self.reset = CSRStorage()
-        self.shoot = CSR()
+        self.reset = CSR()
+        self.start = CSR()
         self.done = CSRStatus()
         self.base = CSRStorage(dram_port.aw)
         self.length = CSRStorage(dram_port.aw)
@@ -95,20 +97,20 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
         self.submodules.core = ClockDomainsRenamer(cd)(core)
 
         reset_sync = BusSynchronizer(1, "sys", cd)
-        shoot_sync = PulseSynchronizer("sys", cd)
+        start_sync = PulseSynchronizer("sys", cd)
         done_sync = BusSynchronizer(1, cd, "sys")
-        self.submodules += reset_sync, shoot_sync, done_sync
+        self.submodules += reset_sync, start_sync, done_sync
 
         base_sync = BusSynchronizer(dram_port.aw, "sys", cd)
         length_sync = BusSynchronizer(dram_port.aw, "sys", cd)
         self.submodules += base_sync, length_sync
 
         self.comb += [
-            reset_sync.i.eq(self.reset.storage),
+            reset_sync.i.eq(self.reset.re),
             core.reset.eq(reset_sync.o),
 
-            shoot_sync.i.eq(self.shoot.re),
-            core.shoot.eq(shoot_sync.o),
+            start_sync.i.eq(self.start.re),
+            core.start.eq(start_sync.o),
 
             done_sync.i.eq(core.done),
             self.done.status.eq(done_sync.o),
@@ -123,7 +125,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
 
 class _LiteDRAMBISTChecker(Module, AutoCSR):
     def __init__(self, dram_port, random):
-        self.shoot = Signal()
+        self.start = Signal()
         self.done = Signal()
         self.base = Signal(dram_port.aw)
         self.length = Signal(dram_port.aw)
@@ -138,21 +140,21 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
         else:
         	self.submodules.gen = gen = Counter(dram_port.dw)
 
-        shooted = Signal()
+        started = Signal()
         address_counter = Signal(dram_port.aw)
         address_counter_ce = Signal()
         data_counter = Signal(dram_port.aw)
         data_counter_ce = Signal()
         self.sync += [
-            If(self.shoot,
-                shooted.eq(1)
+            If(self.start,
+                started.eq(1)
             ),
-            If(self.shoot,
+            If(self.start,
                 address_counter.eq(0)
             ).Elif(address_counter_ce,
                 address_counter.eq(address_counter + 1)
             ),
-            If(self.shoot,
+            If(self.start,
                 data_counter.eq(0),
             ).Elif(data_counter_ce,
                 data_counter.eq(data_counter + 1)
@@ -160,7 +162,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
         ]
 
         address_enable = Signal()
-        self.comb += address_enable.eq(shooted & (address_counter != (self.length - 1)))
+        self.comb += address_enable.eq(started & (address_counter != (self.length - 1)))
 
         self.comb += [
             dma.sink.valid.eq(address_enable),
@@ -169,7 +171,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
         ]
 
         data_enable = Signal()
-        self.comb += data_enable.eq(shooted & (data_counter != (self.length - 1)))
+        self.comb += data_enable.eq(started & (data_counter != (self.length - 1)))
 
         self.comb += [
             gen.ce.eq(dma.source.valid),
@@ -188,8 +190,8 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
 
 class LiteDRAMBISTChecker(Module, AutoCSR):
     def __init__(self, dram_port, random=True):
-        self.reset = CSRStorage()
-        self.shoot = CSR()
+        self.reset = CSR()
+        self.start = CSR()
         self.done = CSRStatus()
         self.base = CSRStorage(dram_port.aw)
         self.length = CSRStorage(dram_port.aw)
@@ -203,9 +205,9 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
         self.submodules.core = ClockDomainsRenamer(cd)(core)
 
         reset_sync = BusSynchronizer(1, "sys", cd)
-        shoot_sync = PulseSynchronizer("sys", cd)
+        start_sync = PulseSynchronizer("sys", cd)
         done_sync = BusSynchronizer(1, cd, "sys")
-        self.submodules += reset_sync, shoot_sync, done_sync
+        self.submodules += reset_sync, start_sync, done_sync
 
         base_sync = BusSynchronizer(dram_port.aw, "sys", cd)
         length_sync = BusSynchronizer(dram_port.aw, "sys", cd)
@@ -216,8 +218,8 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
             reset_sync.i.eq(self.reset.re),
             core.reset.eq(reset_sync.o),
 
-            shoot_sync.i.eq(self.shoot.re),
-            core.shoot.eq(shoot_sync.o),
+            start_sync.i.eq(self.start.re),
+            core.start.eq(start_sync.o),
 
             done_sync.i.eq(core.done),
             self.done.status.eq(done_sync.o),