test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
This commit is contained in:
Florent Kermarrec
parent
329c9904f7
commit
39178ce460
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`ifndef GLBL
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`define GLBL
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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wire FCSBO_GLBL;
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wire [3:0] DO_GLBL;
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wire [3:0] DI_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (weak1, weak0) GSR = GSR_int;
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assign (weak1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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`endif
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "", [("clk", 0, Pins("X"))])
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class OSERDESE2Sim(Module):
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def __init__(self, platform):
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# Clocking
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk"), 100e6)
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pll.create_clkout(self.cd_sys, 100e6)
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pll.create_clkout(self.cd_sys4x, 400e6)
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# OSERDESE2
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i_d = Signal(8)
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i_t1 = Signal()
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o_tq = Signal()
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o_oq = Signal()
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self.specials += Instance("OSERDESE2",
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p_SERDES_MODE = "MASTER",
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p_DATA_WIDTH = 8,
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p_TRISTATE_WIDTH = 1,
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p_DATA_RATE_OQ = "DDR",
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p_DATA_RATE_TQ = "BUF",
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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**{f"i_D{n+1}": i_d[n] for n in range(8)},
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i_TCE = 1,
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i_T1 = ~i_t1,
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o_TQ = o_tq,
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i_OCE = 1,
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o_OQ = o_oq,
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)
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# Stimulation
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counter = Signal(16)
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self.sync += [
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counter.eq(counter + 1),
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If(counter == (16 - 1),
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counter.eq(0)
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),
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If(counter == 0,
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i_d.eq(0xff),
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i_t1.eq(0b0),
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).Else(
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i_d.eq(0x00),
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i_t1.eq(0b1),
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)
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]
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def generate_top():
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platform = Platform()
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sim = OSERDESE2Sim(platform)
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platform.build(sim, build_dir="./", run=False)
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def generate_top_tb():
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f = open("top_tb.v", "w")
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f.write("""
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`timescale 1ns/1ps
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module top_tb();
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reg clk;
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initial clk = 1'b1;
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always #5 clk = ~clk;
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top dut (
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.clk(clk)
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);
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endmodule""")
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f.close()
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def run_sim(gui=False):
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os.system("xvlog glbl.v")
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os.system("xvlog top.v -sv")
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os.system("xvlog top_tb.v -sv")
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os.system("xelab -debug typical top_tb glbl -s top_tb_sim -L unisims_ver -L unimacro_ver -L SIMPRIM_VER -L secureip -L $xsimdir/xil_defaultlib -timescale 1ns/1ps")
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if gui:
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os.system("xsim top_tb_sim -gui")
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else:
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os.system("xsim top_tb_sim -runall")
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def main():
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generate_top()
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generate_top_tb()
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run_sim(gui="gui" in sys.argv[1:])
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if __name__ == "__main__":
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main()
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@ -0,0 +1,112 @@
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "", [("clk", 0, Pins("X"))])
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class OSERDESE3Sim(Module):
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def __init__(self, platform):
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# Clocking
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain()
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self.submodules.pll = pll = USPLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk"), 100e6)
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pll.create_clkout(self.cd_sys, 100e6)
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pll.create_clkout(self.cd_sys4x, 400e6)
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# OSERDESE3
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i_d = Signal(8)
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i_t = Signal()
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o_t_out = Signal()
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o_oq = Signal()
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self.specials += Instance("OSERDESE3",
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p_SIM_DEVICE = "ULTRASCALE",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_T = ~i_t,
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i_D = i_d,
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o_OQ = o_oq,
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o_T_OUT = o_t_out,
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),
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# Stimulation
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counter = Signal(16)
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self.sync += [
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counter.eq(counter + 1),
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If(counter == (16 - 1),
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counter.eq(0)
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),
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If(counter == 0,
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i_d.eq(0xff),
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i_t.eq(0b0),
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).Else(
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i_d.eq(0x00),
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i_t.eq(0b1),
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)
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]
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def generate_top():
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platform = Platform()
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sim = OSERDESE3Sim(platform)
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platform.build(sim, build_dir="./", run=False)
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def generate_top_tb():
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f = open("top_tb.v", "w")
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f.write("""
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`timescale 1ns/1ps
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module top_tb();
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reg clk;
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initial clk = 1'b1;
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always #5 clk = ~clk;
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top dut (
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.clk(clk)
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);
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endmodule""")
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f.close()
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def run_sim(gui=False):
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os.system("xvlog glbl.v")
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os.system("xvlog top.v -sv")
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os.system("xvlog top_tb.v -sv")
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os.system("xelab -debug typical top_tb glbl -s top_tb_sim -L unisims_ver -L unimacro_ver -L SIMPRIM_VER -L secureip -L $xsimdir/xil_defaultlib -timescale 1ns/1ps")
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if gui:
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os.system("xsim top_tb_sim -gui")
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else:
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os.system("xsim top_tb_sim -runall")
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def main():
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generate_top()
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generate_top_tb()
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run_sim(gui="gui" in sys.argv[1:])
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if __name__ == "__main__":
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main()
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