From 394a49a759d3974fc5e3a114a9023d65df808676 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Jul 2019 12:39:43 +0200 Subject: [PATCH] test: add test_timing_controllers with tXXDController test --- test/test_timing_controllers.py | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 test/test_timing_controllers.py diff --git a/test/test_timing_controllers.py b/test/test_timing_controllers.py new file mode 100644 index 0000000..7a3f365 --- /dev/null +++ b/test/test_timing_controllers.py @@ -0,0 +1,40 @@ +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + +import unittest +import random + +from migen import * + +from litedram.common import tXXDController + +class TestTimingControllers(unittest.TestCase): + def txxd_controller_test(self, txxd, loops): + def generator(dut, valid_rand): + prng = random.Random(42) + for l in range(loops): + while prng.randrange(100) < valid_rand: + yield + yield dut.valid.eq(1) + yield + yield dut.valid.eq(0) + + @passive + def checker(dut): + dut.ready_gaps = [] + while True: + while (yield dut.ready) != 0: + yield + ready_gap = 1 + while (yield dut.ready) != 1: + ready_gap += 1 + yield + dut.ready_gaps.append(ready_gap) + + dut = tXXDController(txxd) + run_simulation(dut, [generator(dut, valid_rand=90), checker(dut)]) + self.assertEqual(min(dut.ready_gaps), txxd) + + def test_txxd_controller(self): + for i in range(2, 32): + self.txxd_controller_test(i, 512)